| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | floating_point.json | 30 "BriefDescription": "Single Precision floating point instruction completed."
40 …"BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres,…
45 "BriefDescription": "Four Double Precision vector instruction completed."
65 "BriefDescription": "Double-Precision or Quad-Precision instruction completed."
|
| /kernel/linux/linux-6.6/arch/parisc/math-emu/ |
| D | fpudispatch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
52 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
73 * the following are for the multi-ops
106 * positions 21-22
111 * located at bit positions 16-18
116 * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0)
160 /* on pa-linux the fpu type is not filled in by the in parisc_linux_get_fpu_type()
[all …]
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| D | float.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
26 PA header file -- do not include this header file for non-PA builds.
41 * floating-point precisions.
44 * +-------+-------+-------+-------+-------+-------+-------+-------+
46 * +-------+-------+-------+-------+-------+-------+-------+-------+
97 * +-------+-------+-------+-------+-------+-------+-------+-------+
99 * +-------+-------+-------+-------+-------+-------+-------+-------+
[all …]
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| /kernel/linux/linux-5.10/arch/parisc/math-emu/ |
| D | fpudispatch.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
52 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1))
73 * the following are for the multi-ops
106 * positions 21-22
111 * located at bit positions 16-18
116 * at bit positions 15-16 (PA1.1) or 14-16 (PA2.0)
160 /* on pa-linux the fpu type is not filled in by the in parisc_linux_get_fpu_type()
[all …]
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| D | float.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
26 PA header file -- do not include this header file for non-PA builds.
41 * floating-point precisions.
44 * +-------+-------+-------+-------+-------+-------+-------+-------+
46 * +-------+-------+-------+-------+-------+-------+-------+-------+
97 * +-------+-------+-------+-------+-------+-------+-------+-------+
99 * +-------+-------+-------+-------+-------+-------+-------+-------+
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | vector.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <asm/asm-offsets.h>
12 #include <asm/asm-compat.h>
47 * Note that on 32-bit this can only use registers that will be
48 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
69 li r4,-1
119 #error This asm code isn't ready for 32-bit kernels
158 * usage of floating-point registers. These routines must be called
166 .long 0x3f800000 /* 1.0 in single-precision FP */
168 .long 0x3f000000 /* 0.5 in single-precision FP */
[all …]
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| /kernel/linux/linux-6.6/Documentation/powerpc/ |
| D | elf_hwcaps.rst | 11 ---------------
46 -------------
56 -------------
65 -------------------
67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
71 ---------------------------------
74 32-bit CPU
77 64-bit CPU (userspace may be running in 32-bit mode).
104 Embedded Floating Point single precision operations are available.
107 Embedded Floating Point double precision operations are available.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
115 …cause the NTF instruction was a vector instruction issued to the Double Precision execution pipe a…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
170 "BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
220 …stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precis…
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
115 …cause the NTF instruction was a vector instruction issued to the Double Precision execution pipe a…
130 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
140 …"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this t…
170 "BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
220 …stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precis…
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/ice/ |
| D | ice_ptp_hw.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * for the Precision Time Protocol.
16 * +---------------+ +---------------+ +---------------+
18 * +---------------+ +---------------+ +---------------+
24 * +---------------+ +---------------+
26 * +---------------+ +---------------+
37 * - 823.4375 MHz
38 * - 783.36 MHz
39 * - 796.875 MHz
40 * - 816 MHz
[all …]
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| /kernel/linux/linux-6.6/include/math-emu/ |
| D | quad.h | 1 /* Software floating-point emulation.
2 Definitions for IEEE Quad Precision.
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
39 #define _FP_FRACXBITS_Q (_FP_FRACTBITS_Q - _FP_FRACBITS_Q)
41 #define _FP_WFRACXBITS_Q (_FP_FRACTBITS_Q - _FP_WFRACBITS_Q)
47 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-2) % _FP_W_TYPE_SIZE)
49 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-1) % _FP_W_TYPE_SIZE)
63 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
71 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
141 unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE;
[all …]
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| /kernel/linux/linux-5.10/include/math-emu/ |
| D | quad.h | 1 /* Software floating-point emulation.
2 Definitions for IEEE Quad Precision.
23 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
39 #define _FP_FRACXBITS_Q (_FP_FRACTBITS_Q - _FP_FRACBITS_Q)
41 #define _FP_WFRACXBITS_Q (_FP_FRACTBITS_Q - _FP_WFRACBITS_Q)
47 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-2) % _FP_W_TYPE_SIZE)
49 ((_FP_W_TYPE)1 << (_FP_FRACBITS_Q-1) % _FP_W_TYPE_SIZE)
63 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
71 unsigned long frac3 : _FP_FRACBITS_Q - (_FP_IMPLBIT_Q != 0)-(_FP_W_TYPE_SIZE * 3);
141 unsigned long frac1 : _FP_FRACBITS_Q-(_FP_IMPLBIT_Q != 0)-_FP_W_TYPE_SIZE;
[all …]
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| /kernel/linux/linux-6.6/drivers/staging/media/ipu3/include/uapi/ |
| D | intel-ipu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
119 * struct ipu3_uapi_awb_config_s - AWB config
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/media/ipu3/include/ |
| D | intel-ipu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
15 /* from include/uapi/linux/v4l2-controls.h */
24 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
32 * struct ipu3_uapi_grid_config - Grid plane config
48 * create a grid-based output, and the data is then divided into "slices".
79 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
90 * struct ipu3_uapi_awb_config_s - AWB config
110 * struct ipu3_uapi_awb_config - AWB config wrapper
[all …]
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| /kernel/linux/linux-6.6/lib/ |
| D | vsprintf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 /* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
10 * Wirzenius wrote this portably, Torvalds fucked it up :-)
15 * - changed to provide snprintf and vsnprintf functions
17 * - scnprintf and vscnprintf
23 #include <linux/clk-provider.h>
71 prefix_chars = cp - startp; in simple_strntoull()
73 rv = _parse_integer_limit(cp, base, &result, max_chars - prefix_chars); in simple_strntoull()
88 * simple_strtoull - convert a string to an unsigned long long
103 * simple_strtoul - convert a string to an unsigned long
[all …]
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| /kernel/linux/linux-5.10/lib/ |
| D | vsprintf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 /* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
10 * Wirzenius wrote this portably, Torvalds fucked it up :-)
15 * - changed to provide snprintf and vsnprintf functions
17 * - scnprintf and vscnprintf
23 #include <linux/clk-provider.h>
65 prefix_chars = cp - startp; in simple_strntoull()
67 rv = _parse_integer_limit(cp, base, &result, max_chars - prefix_chars); in simple_strntoull()
82 * simple_strtoull - convert a string to an unsigned long long
96 * simple_strtoul - convert a string to an unsigned long
[all …]
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| /kernel/linux/linux-6.6/Documentation/networking/ |
| D | phy.rst | 26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
99 precision may be required to account for differences in PCB trace lengths
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
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| /kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/ |
| D | core_feature_base.h | 4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
47 /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
69 …rv_csr_t b:1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation…
71 …rv_csr_t d:1; /*!< bit: 3 Double-precision floating-point extension…
73 …rv_csr_t f:1; /*!< bit: 5 Single-precision floating-point extension…
79 … /*!< bit: 11 Tentatively reserved for Decimal Floating-Point extension */
81 rv_csr_t n:1; /*!< bit: 13 User-level interrupts supported */
83 …rv_csr_t p:1; /*!< bit: 15 Tentatively reserved for Packed-SIMD exte…
84 …rv_csr_t q:1; /*!< bit: 16 Quad-precision floating-point extension …
[all …]
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| /kernel/linux/linux-5.10/tools/arch/x86/include/asm/ |
| D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 20 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
[all …]
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
[all …]
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| /kernel/linux/linux-6.6/tools/arch/x86/include/asm/ |
| D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 21 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
[all …]
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| /kernel/linux/linux-6.6/arch/x86/include/asm/ |
| D | cpufeatures.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
[all …]
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| /kernel/linux/linux-6.6/sound/pci/hda/ |
| D | patch_realtek.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
35 /* extra amp-initialization sequence types */
146 struct alc_spec *spec = codec->spec; in coef_mutex_lock()
149 mutex_lock(&spec->coef_mutex); in coef_mutex_lock()
154 struct alc_spec *spec = codec->spec; in coef_mutex_unlock()
156 mutex_unlock(&spec->coef_mutex); in coef_mutex_unlock()
208 if (val != -1) in __alc_update_coefex_idx()
228 struct alc_spec *spec = codec->spec; in alc_get_coef0()
230 if (!spec->coef0) in alc_get_coef0()
231 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0()
[all …]
|