| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-emc.txt | 4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
20 memory-controller@7000f400 {
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| /kernel/linux/linux-6.6/include/linux/ |
| D | hp_sdc.h | 2 * HP i8042 System Device Controller -- header
10 * 1. Redistributions of source code must retain the above copyright
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
149 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
150 #define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
151 #define HP_SDC_CFG_REV 0x40 /* Code revision bit */
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| /kernel/linux/linux-5.10/include/linux/ |
| D | hp_sdc.h | 2 * HP i8042 System Device Controller -- header
10 * 1. Redistributions of source code must retain the above copyright
31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
104 #define HP_SDC_STATUS_PUP 0x70 /* Successful power-up self test */
134 #define HP_SDC_STR 0x7f /* i8042 self-test result */
146 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
149 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
150 #define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
151 #define HP_SDC_CFG_REV 0x40 /* Code revision bit */
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | porting.rst | 5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
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| D | tcm.rst | 2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
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| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | porting.rst | 5 Taken from list archive at http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2001-July/00406…
8 -------------------
14 phys = virt - PAGE_OFFSET + PHYS_OFFSET
18 --------------------
23 the time when you call the decompressor code. You normally call
25 to be located in RAM, it can be in flash or other read-only or
26 read-write addressable medium.
29 Start address of zero-initialised work area for the decompressor.
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
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| D | tcm.rst | 2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
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| /kernel/linux/linux-5.10/drivers/net/ethernet/amd/ |
| D | mvme147.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Uses the generic 7990.c LANCE code.
30 /* We have 32K of RAM for the init block and buffers. This places
37 #include "7990.h" /* use generic LANCE code */
42 unsigned long ram; member
47 * plus board-specific init, open and close actions.
48 * Oh, and we need to tell the generic code how to read and write LANCE registers...
70 /* Initialise the one and only on-board 7990 */
82 return ERR_PTR(-ENODEV); in mvme147lance_probe()
87 return ERR_PTR(-ENOMEM); in mvme147lance_probe()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/amd/ |
| D | mvme147.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Uses the generic 7990.c LANCE code.
30 /* We have 32K of RAM for the init block and buffers. This places
37 #include "7990.h" /* use generic LANCE code */
42 unsigned long ram; member
47 * plus board-specific init, open and close actions.
48 * Oh, and we need to tell the generic code how to read and write LANCE registers...
70 /* Initialise the one and only on-board 7990 */
83 return ERR_PTR(-ENODEV); in mvme147lance_probe()
88 return ERR_PTR(-ENOMEM); in mvme147lance_probe()
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| /kernel/linux/linux-6.6/drivers/net/ethernet/intel/i40e/ |
| D | i40e_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
10 * i40e_init_nvm - Initialize NVM function pointers
17 * We are accessing FLASH always thru the Shadow RAM.
21 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
33 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
39 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
40 nvm->blank_nvm_mode = false; in i40e_init_nvm()
42 nvm->blank_nvm_mode = true; in i40e_init_nvm()
43 ret_code = -EIO; in i40e_init_nvm()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/i40e/ |
| D | i40e_nvm.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 * i40e_init_nvm_ops - Initialize NVM function pointers
14 * We are accessing FLASH always thru the Shadow RAM.
18 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
30 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
36 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
37 nvm->blank_nvm_mode = false; in i40e_init_nvm()
39 nvm->blank_nvm_mode = true; in i40e_init_nvm()
48 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
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| /kernel/linux/linux-5.10/Documentation/vm/ |
| D | frontswap.rst | 9 swapped pages are saved in RAM (or a RAM-like device) instead of a swap disk.
11 (Note, frontswap -- and :ref:`cleancache` (merged at 3.0) -- are the "frontends"
13 all other supporting code -- the "backends" -- is implemented as drivers.
21 a synchronous concurrency-safe page-oriented "pseudo-RAM device" conforming
23 in-kernel compressed memory, aka "zcache", or future RAM-like devices);
24 this pseudo-RAM device is not directly accessible or addressable by the
25 kernel and is of unknown and possibly time-varying size. The driver
50 in swap device writes is lost (and also a non-trivial performance advantage)
88 useful for write-balancing for some RAM-like devices). Swap pages (and
89 evicted page-cache pages) are a great use for this kind of slower-than-RAM-
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| D | cleancache.rst | 14 Cleancache can be thought of as a page-granularity victim cache for clean
17 PFRA "evicts" a page, it first attempts to use cleancache code to
20 of unknown and possibly time-varying size.
22 Later, when a cleancache-enabled filesystem wishes to access a page
28 in Xen (using hypervisor memory) and zcache (using in-kernel compressed
48 Mounting a cleancache-enabled filesystem should call "init_fs" to obtain a
51 (presumably about-to-be-evicted) page into cleancache and associate it with
62 to treat the pool as shared using a 128-bit UUID as a key. On systems
72 If a get_page is successful on a non-shared pool, the page is invalidated
79 Note that cleancache must enforce put-put-get coherency and get-get
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| /kernel/linux/linux-5.10/arch/m68k/ |
| D | Kconfig.machine | 1 # SPDX-License-Identifier: GPL-2.0
21 This option enables support for the 68000-based Atari series of
39 Say N unless you're willing to code the remaining necessary support.
47 Say Y here if you want to run Linux on an MC680x0-based Apollo
66 build a kernel which can run on MVME147 single-board computers. If
121 The Q40 is a Motorola 68040-based successor to the Sinclair QL
274 Support for the Sysam AMCORE open-hardware generic board.
280 Support for the Sysam stmark2 open-hardware generic board.
313 bool "Netburner MOD-5272 board support"
316 Support for the Netburner MOD-5272 board.
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
17 various performance-affecting settings beyond the obvious SDRAM configuration
23 const: nvidia,tegra20-emc
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | tcm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson AB
41 .name = "DTCM RAM",
48 .name = "ITCM RAM",
114 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, in setup_tcm_bank()
115 256, 512, 1024, -1, -1, -1, -1 }; in setup_tcm_bank()
141 return -EINVAL; in setup_tcm_bank()
145 return -EINVAL; in setup_tcm_bank()
183 * When we are running in the non-secure world and the secure world
200 * In this particular case (MRC with ARM condition code ALways) the
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | tcm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2008-2009 ST-Ericsson AB
41 .name = "DTCM RAM",
48 .name = "ITCM RAM",
114 const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128, in setup_tcm_bank()
115 256, 512, 1024, -1, -1, -1, -1 }; in setup_tcm_bank()
141 return -EINVAL; in setup_tcm_bank()
145 return -EINVAL; in setup_tcm_bank()
183 * When we are running in the non-secure world and the secure world
200 * In this particular case (MRC with ARM condition code ALways) the
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| /kernel/linux/linux-6.6/arch/x86/kernel/ |
| D | ebda.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * are code), that must not be used by the kernel as available
13 * RAM.
20 * guess the reserved BIOS area by looking at the low BIOS RAM size
26 * - This code also contains a quirk for Dell systems that neglect
27 * to reserve the EBDA area in the 'RAM size' value ...
29 * - The same quirk also avoids a problem with the AMD768MPX
34 * - Plus paravirt systems don't have a reliable value in the
35 * 'BIOS RAM size' pointer we can rely on, so we must quirk
70 * BIOS RAM size is encoded in kilobytes, convert it in reserve_bios_regions()
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| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | ebda.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * are code), that must not be used by the kernel as available
13 * RAM.
20 * guess the reserved BIOS area by looking at the low BIOS RAM size
26 * - This code also contains a quirk for Dell systems that neglect
27 * to reserve the EBDA area in the 'RAM size' value ...
29 * - The same quirk also avoids a problem with the AMD768MPX
34 * - Plus paravirt systems don't have a reliable value in the
35 * 'BIOS RAM size' pointer we can rely on, so we must quirk
70 * BIOS RAM size is encoded in kilobytes, convert it in reserve_bios_regions()
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| /kernel/linux/linux-6.6/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
24 /* Actual code that puts the SoC in different idle states */
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013 Xilinx
7 * based on arch/arm/mach-at91/cpuidle.c
9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
10 * to implement two idle states -
11 * #1 wait-for-interrupt
12 * #2 wait-for-interrupt and RAM self refresh
24 /* Actual code that puts the SoC in different idle states */
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /kernel/linux/linux-6.6/drivers/block/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 drivers. This option alone does not add any kernel code.
28 <file:Documentation/admin-guide/blockdev/floppy.rst>.
41 special low-level hardware accesses to them (access and use
42 non-standard formats, for example), then enable this.
44 Note that the code enabled by this option is rarely used and
64 If you have a SWIM-3 (Super Woz Integrated Machine 3; from Apple)
78 This enables support for using Chip RAM and Zorro II RAM as a
95 tristate "SEGA Dreamcast GD-ROM drive"
100 "GD-ROM" by SEGA to signify it is capable of reading special disks
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| /kernel/linux/linux-6.6/kernel/power/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Suspend to RAM and standby"
9 suspend-to-RAM state (e.g. the ACPI S3 state).
12 bool "Enable freezer for suspend to RAM/standby" \
18 done, no tasks are frozen for suspend to RAM/standby.
23 bool "Skip kernel's sys_sync() on suspend to RAM/standby"
30 user-space before invoking suspend. There's a run-time switch
32 This setting changes the default for the run-tim switch. Say Y
60 for suspend states like suspend-to-RAM (STR) often don't work very
72 <file:Documentation/power/swsusp-and-swap-files.rst>).
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| /kernel/linux/linux-6.6/arch/m68k/atari/ |
| D | stram.c | 2 * Functions for ST-RAM allocations
4 * Copyright 1994-97 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
35 * The ST-RAM allocator allocates memory from a pool of reserved ST-RAM of
36 * configurable size, set aside on ST-RAM init.
37 * As long as this pool is not exhausted, allocation of real ST-RAM can be
41 /* set if kernel is in ST-RAM */
45 .name = "ST-RAM Pool"
73 * determine whether kernel code resides in ST-RAM in atari_stram_init()
74 * (then ST-RAM is the first memory block at virtual 0x0) in atari_stram_init()
84 /* Should never come here! (There is always ST-Ram!) */ in atari_stram_init()
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| /kernel/linux/linux-5.10/arch/m68k/atari/ |
| D | stram.c | 2 * Functions for ST-RAM allocations
4 * Copyright 1994-97 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
35 * The ST-RAM allocator allocates memory from a pool of reserved ST-RAM of
36 * configurable size, set aside on ST-RAM init.
37 * As long as this pool is not exhausted, allocation of real ST-RAM can be
41 /* set if kernel is in ST-RAM */
45 .name = "ST-RAM Pool"
73 * determine whether kernel code resides in ST-RAM in atari_stram_init()
74 * (then ST-RAM is the first memory block at virtual 0x0) in atari_stram_init()
84 /* Should never come here! (There is always ST-Ram!) */ in atari_stram_init()
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