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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/
Dmax8952.txt4 - compatible: must be equal to "maxim,max8952"
5 - reg: I2C slave address, usually 0x60
6 - max8952,dvs-mode-microvolt: array of 4 integer values defining DVS voltages
8 - any required generic properties defined in regulator.txt
11 - max8952,vid-gpios: array of two GPIO pins used for DVS voltage selection
12 - max8952,en-gpio: GPIO used to control enable status of regulator
13 - max8952,default-mode: index of default DVS voltage, from <0, 3> range
14 - max8952,sync-freq: sync frequency, must be one of following values:
15 - 0: 26 MHz
16 - 1: 13 MHz
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
45 Voltage ramp speed, values map to:
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsdm670-google-sargo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
4 * xiaomi-lavender device tree, and oneplus-common device tree.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
19 /delete-node/ &mpss_region;
20 /delete-node/ &venus_mem;
[all …]
Dsda660-inforce-ifc6560.dts1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
18 chassis-type = "embedded"; /* SBC */
26 stdout-path = "serial0:115200n8";
29 gpio-keys {
30 compatible = "gpio-keys";
32 key-volup {
36 debounce-interval = <15>;
41 * Until we hook up type-c detection, we
44 extcon_usb: extcon-usb {
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/
Dhi3660-hikey960.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include "hikey960-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/usb/pd.h>
20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
35 stdout-path = "serial6:115200n8";
44 reserved-memory {
[all …]
Dhi6220-hikey.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "hikey-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
26 stdout-path = "serial3:115200n8";
32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi3660-hikey960.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include "hikey960-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/usb/pd.h>
20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
35 stdout-path = "serial6:115200n8";
44 reserved-memory {
[all …]
Dhi6220-hikey.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "hikey-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
26 stdout-path = "serial3:115200n8";
32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason
34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data
35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section
[all …]
/kernel/linux/linux-6.6/Documentation/hwmon/
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
/kernel/linux/linux-5.10/Documentation/hwmon/
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
[all …]
/kernel/linux/linux-6.6/drivers/cpufreq/
Dpmac64-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
41 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
42 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
43 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
44 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
57 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
61 * The G5 only supports two frequencies (Quarter speed is not supported)
73 * the various frequencies, retrieved from the device-tree
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Dpmac64-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
4 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
41 #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
42 #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
43 #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
44 #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
57 #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
61 * The G5 only supports two frequencies (Quarter speed is not supported)
73 * the various frequencies, retrieved from the device-tree
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/renesas/
Dr8a7745-iwg22d-sodimm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E SODIMM carrier board
9 * SSI-SGTL5000
21 * You can use Volume Ramp
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
31 /dts-v1/;
32 #include "r8a7745-iwg22m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dr8a7745-iwg22d-sodimm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E SODIMM carrier board
9 * SSI-SGTL5000
21 * You can use Volume Ramp
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
31 /dts-v1/;
32 #include "r8a7745-iwg22m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
[all …]
/kernel/linux/linux-5.10/drivers/regulator/
Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
42 /* check whether need to care about LDO ramp up speed */ in anatop_regmap_set_voltage_time_sel()
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
45 * the delay for LDO ramp up time is in anatop_regmap_set_voltage_time_sel()
48 * ramp up, and how much delay needed. (us) in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
[all …]
Dmax8952.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max8952.c - Voltage and current regulation for the Maxim 8952
46 int ret = i2c_smbus_read_byte_data(max8952->client, reg); in max8952_read_reg()
57 return i2c_smbus_write_byte_data(max8952->client, reg, value); in max8952_write_reg()
66 return -EINVAL; in max8952_list_voltage()
68 return (max8952->pdata->dvs_mode[selector] * 10 + 770) * 1000; in max8952_list_voltage()
76 if (max8952->vid0) in max8952_get_voltage_sel()
78 if (max8952->vid1) in max8952_get_voltage_sel()
89 if (!max8952->vid0_gpiod || !max8952->vid1_gpiod) { in max8952_set_voltage_sel()
91 return -EPERM; in max8952_set_voltage_sel()
[all …]
/kernel/linux/linux-6.6/drivers/regulator/
Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
42 /* check whether need to care about LDO ramp up speed */ in anatop_regmap_set_voltage_time_sel()
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
45 * the delay for LDO ramp up time is in anatop_regmap_set_voltage_time_sel()
48 * ramp up, and how much delay needed. (us) in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
[all …]
Dmax8952.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max8952.c - Voltage and current regulation for the Maxim 8952
46 int ret = i2c_smbus_read_byte_data(max8952->client, reg); in max8952_read_reg()
57 return i2c_smbus_write_byte_data(max8952->client, reg, value); in max8952_write_reg()
66 return -EINVAL; in max8952_list_voltage()
68 return (max8952->pdata->dvs_mode[selector] * 10 + 770) * 1000; in max8952_list_voltage()
76 if (max8952->vid0) in max8952_get_voltage_sel()
78 if (max8952->vid1) in max8952_get_voltage_sel()
89 if (!max8952->vid0_gpiod || !max8952->vid1_gpiod) { in max8952_set_voltage_sel()
91 return -EPERM; in max8952_set_voltage_sel()
[all …]
/kernel/linux/linux-6.6/drivers/soc/qcom/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
15 the low-power state for resources related to the remoteproc
26 resource on a RPM-hardened platform must use this database to get
43 be called qcom-cpr
110 Say yes here to support USB-C and battery status on modern Qualcomm
118 tristate "Qualcomm Ramp Controller driver"
121 The Ramp Controller is used to program the sequence ID for pulse
124 Say y here to enable support for the ramp controller.
133 purpose of exchanging sector-data between the remote filesystem
142 The RPM Master sleep stats driver provides detailed per-subsystem
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dvc.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "prm-regbits-34xx.h"
20 #include "prm-regbits-44xx.h"
52 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
101 * omap_vc_config_channel - configure VC channel to PMIC mappings
106 * - i2c slave address (SA)
107 * - voltage configuration address (RAV)
108 * - command configuration address (RAC) and enable bit (RACEN)
109 * - command values for ON, ONLP, RET and OFF (CMD)
112 * non-default channel. Starting with OMAP4, there are more than 2
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dvc.c22 #include "prm-regbits-34xx.h"
23 #include "prm-regbits-44xx.h"
55 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
104 * omap_vc_config_channel - configure VC channel to PMIC mappings
109 * - i2c slave address (SA)
110 * - voltage configuration address (RAV)
111 * - command configuration address (RAC) and enable bit (RACEN)
112 * - command values for ON, ONLP, RET and OFF (CMD)
115 * non-default channel. Starting with OMAP4, there are more than 2
117 * Only the non-default channel can be configured.
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
21 stdout-path = "serial0:115200n8";
25 compatible = "hdmi-connector";
26 ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
31 remote-endpoint = <&hdmi_out_con>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 /dts-v1/;
6 #include "sun50i-h6.dtsi"
7 #include "sun50i-h6-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
21 stdout-path = "serial0:115200n8";
25 compatible = "hdmi-connector";
26 ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
31 remote-endpoint = <&hdmi_out_con>;
[all …]

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