| /kernel/linux/linux-5.10/include/soc/at91/ |
| D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl…
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
[all …]
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| /kernel/linux/linux-6.6/include/soc/at91/ |
| D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
48 #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Onl…
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
[all …]
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| /kernel/linux/linux-5.10/drivers/iio/common/ms_sensors/ |
| D | ms_sensors_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015 Measurement-Specialties
11 #include <linux/delay.h>
38 * ms_sensors_reset() - Reset function
41 * @delay: usleep minimal delay after reset command is issued
47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument
54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset()
57 usleep_range(delay, delay + 1000); in ms_sensors_reset()
64 * ms_sensors_read_prom_word() - PROM word read function
66 * @cmd: PROM read cmd. Depends on device and prom id
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| D | ti,gpmc-child.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
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| /kernel/linux/linux-6.6/drivers/iio/common/ms_sensors/ |
| D | ms_sensors_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2015 Measurement-Specialties
11 #include <linux/delay.h>
38 * ms_sensors_reset() - Reset function
41 * @delay: usleep minimal delay after reset command is issued
47 int ms_sensors_reset(void *cli, u8 cmd, unsigned int delay) in ms_sensors_reset() argument
54 dev_err(&client->dev, "Failed to reset device\n"); in ms_sensors_reset()
57 usleep_range(delay, delay + 1000); in ms_sensors_reset()
64 * ms_sensors_read_prom_word() - PROM word read function
66 * @cmd: PROM read cmd. Depends on device and prom id
[all …]
|
| /kernel/linux/linux-6.6/arch/sh/include/mach-common/mach/ |
| D | sh2007.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
40 /* burst count (0-3:4,8,16,32) */
46 /* RD hold for SRAM (0-1:0,1) */
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
52 /* Multiplex (0-1:0,1) */
[all …]
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| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | sh2007.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
34 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
37 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
40 /* burst count (0-3:4,8,16,32) */
46 /* RD hold for SRAM (0-1:0,1) */
49 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
52 /* Multiplex (0-1:0,1) */
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/platforms/pasemi/ |
| D | gpio_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
25 #define DELAY 1 macro
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
78 udelay(DELAY); in clock_out()
80 udelay(DELAY); in clock_out()
84 /* Utility to send the preamble, address, and register (common to read and write). */
85 static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) in bitbang_pre() argument
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/platforms/pasemi/ |
| D | gpio_mdio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
25 #define DELAY 1 macro
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
78 udelay(DELAY); in clock_out()
80 udelay(DELAY); in clock_out()
84 /* Utility to send the preamble, address, and register (common to read and write). */
85 static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) in bitbang_pre() argument
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
|
| /kernel/linux/linux-6.6/Documentation/i2c/ |
| D | slave-testunit-backend.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
23 After that, you will have a write-only device listening. Reads will just return
24 an 8-bit version number of the testunit. When writing, the device consists of 4
25 8-bit registers and, except for some "partial" commands, all registers must be
29 0x00 CMD - which test to trigger
30 0x01 DATAL - configuration byte 1 for the test
31 0x02 DATAH - configuration byte 2 for the test
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/i2c/ |
| D | slave-testunit-backend.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
23 After that, you will have a write-only device listening. Reads will just return
24 an 8-bit version number of the testunit. When writing, the device consists of 4
25 8-bit registers and all must be written to start a testcase, i.e. you must
28 0x00 CMD - which test to trigger
29 0x01 DATAL - configuration byte 1 for the test
30 0x02 DATAH - configuration byte 2 for the test
[all …]
|
| /kernel/linux/linux-6.6/drivers/md/ |
| D | dm-delay.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2007 Red Hat GmbH
17 #include <linux/device-mapper.h>
19 #define DM_MSG_PREFIX "delay"
24 unsigned int delay; member
36 struct delay_class read; member
56 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
61 mutex_lock(&dc->timer_lock); in queue_timeout()
63 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
64 mod_timer(&dc->delay_timer, expires); in queue_timeout()
[all …]
|
| /kernel/linux/linux-5.10/drivers/md/ |
| D | dm-delay.c | 2 * Copyright (C) 2005-2007 Red Hat GmbH
16 #include <linux/device-mapper.h>
18 #define DM_MSG_PREFIX "delay"
23 unsigned delay; member
35 struct delay_class read; member
55 queue_work(dc->kdelayd_wq, &dc->flush_expired_bios); in handle_delayed_timer()
60 mutex_lock(&dc->timer_lock); in queue_timeout()
62 if (!timer_pending(&dc->delay_timer) || expires < dc->delay_timer.expires) in queue_timeout()
63 mod_timer(&dc->delay_timer, expires); in queue_timeout()
65 mutex_unlock(&dc->timer_lock); in queue_timeout()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
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| D | jedec,lpddr3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/ |
| D | rng.c | 27 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read()
28 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_data_read()
50 sc->rng_last = rng_last; in ath9k_rng_data_read()
57 u32 delay; in ath9k_rng_delay_get() local
60 delay = 10; in ath9k_rng_delay_get()
62 delay = 1000; in ath9k_rng_delay_get()
64 delay = 10000; in ath9k_rng_delay_get()
66 return delay; in ath9k_rng_delay_get()
91 bytes_read = -EIO; in ath9k_rng_read()
98 struct ath_hw *ah = sc->sc_ah; in ath9k_rng_start()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
20 Delay for read capture logic, in clock cycles.
[all …]
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| /kernel/linux/linux-5.10/include/linux/reset/ |
| D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
27 * @status_active_low: if true, bits read back as cleared while the reset is
28 * asserted. Otherwise, bits read back as set while the
30 * @reset_us: Minimum delay in microseconds needed that needs to be
32 * device. If multiple consumers with different delay
34 * be the largest minimum delay. 0 means that such a delay is
|
| /kernel/linux/linux-6.6/include/linux/reset/ |
| D | reset-simple.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
27 * @status_active_low: if true, bits read back as cleared while the reset is
28 * asserted. Otherwise, bits read back as set while the
30 * @reset_us: Minimum delay in microseconds needed that needs to be
32 * device. If multiple consumers with different delay
34 * be the largest minimum delay. 0 means that such a delay is
|