| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | cpufreq-utils-s3c24xx.c | 23 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
26 * Set the SDRAM refresh value appropriately for the configured
32 unsigned long refresh; in s3c2410_cpufreq_setrefresh() local
35 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2410_cpufreq_setrefresh()
38 * This should work for HCLK up to 133MHz and refresh period up in s3c2410_cpufreq_setrefresh()
42 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
43 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2410_cpufreq_setrefresh()
44 refresh = (1 << 11) + 1 - refresh; in s3c2410_cpufreq_setrefresh()
46 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); in s3c2410_cpufreq_setrefresh()
50 refval |= refresh; in s3c2410_cpufreq_setrefresh()
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| D | iotiming-s3c2412.c | 260 u32 refresh; in s3c2412_cpufreq_setrefresh() local
264 /* Reduce both the refresh time (in ns) and the frequency (in MHz) in s3c2412_cpufreq_setrefresh()
267 * This should work for HCLK up to 133MHz and refresh period up in s3c2412_cpufreq_setrefresh()
271 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
272 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2412_cpufreq_setrefresh()
273 refresh &= ((1 << 16) - 1); in s3c2412_cpufreq_setrefresh()
275 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); in s3c2412_cpufreq_setrefresh()
277 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
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| /kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 65 @ Setup self-refresh with support for manual exit of
66 @ self-refresh mode
72 @ Wait for self-refresh acknowledge, clocks to the DRAM device
73 @ will automatically stop on start of self-refresh
78 bne 3b @ Branch until self-refresh mode starts
115 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
116 @ update yet. DRAM is still in self-refresh
124 @ Clear self-refresh mode
131 @ Wait for EMC to clear self-refresh mode
135 bne 5b @ Branch until self-refresh has exited
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| D | pm.c | 40 * DRAM refresh
41 * DRAM clocking and refresh are slightly different for systems with DDR
46 * and exit DRAM self-refresh modes must not be executed in DRAM. A small
53 * Places DRAMs in self-refresh mode
128 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
129 * start of self-refresh. This only needs to be done once. in lpc32xx_pm_init()
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| /kernel/linux/linux-6.6/arch/arm/mach-lpc32xx/ |
| D | suspend.S | 63 @ Setup self-refresh with support for manual exit of
64 @ self-refresh mode
70 @ Wait for self-refresh acknowledge, clocks to the DRAM device
71 @ will automatically stop on start of self-refresh
76 bne 3b @ Branch until self-refresh mode starts
113 @ Re-enter run mode with self-refresh flag cleared, but no DRAM
114 @ update yet. DRAM is still in self-refresh
122 @ Clear self-refresh mode
129 @ Wait for EMC to clear self-refresh mode
133 bne 5b @ Branch until self-refresh has exited
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 40 u_short refresh; /* refresh time for array (us) */ member
57 .refresh = 64000,
66 .refresh = 64000,
75 .refresh = 64000,
83 .refresh = 64000,
92 .refresh = 64000,
101 .refresh = 64000,
110 .refresh = 64000,
196 * Set the SDRAM refresh rate.
205 * Update the refresh period. We do this such that we always refresh
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mode and memory controller clock
89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode if bus is idle for
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into self-refresh mode if bus is idle
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
[all …]
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| /kernel/linux/linux-6.6/include/soc/at91/ |
| D | sama7-ddr.h | 55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …FREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic S…
58 …T_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-ref…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
68 #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
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| D | at91sam9_sdramc.h | 26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| /kernel/linux/linux-6.6/drivers/video/fbdev/core/ |
| D | fbcvt.c | 38 u32 refresh; member
230 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
262 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
281 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
288 * @mode is filled with computed values. If interlaced, the refresh field
311 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
312 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
315 if (!cvt.xres || !cvt.yres || !cvt.refresh || cvt.f_refresh > INT_MAX) { in fb_find_mode_cvt()
320 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
321 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/core/ |
| D | fbcvt.c | 38 u32 refresh; member
230 cvt->xres, cvt->yres, cvt->refresh); in fb_cvt_print_name()
262 mode->refresh = cvt->f_refresh; in fb_cvt_convert_to_mode()
281 * @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
288 * @mode is filled with computed values. If interlaced, the refresh field
311 cvt.refresh = mode->refresh; in fb_find_mode_cvt()
312 cvt.f_refresh = cvt.refresh; in fb_find_mode_cvt()
315 if (!cvt.xres || !cvt.yres || !cvt.refresh || cvt.f_refresh > INT_MAX) { in fb_find_mode_cvt()
320 if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 || in fb_find_mode_cvt()
321 cvt.refresh == 85)) { in fb_find_mode_cvt()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 27 * framework to implement panel self refresh (SR) support. Drivers are
32 * (meaning it knows how to initiate self refresh on the panel).
140 * update the average entry/exit self refresh times on self refresh transitions.
142 * entering self refresh mode after activity.
179 * incompatible with self refresh exit and changes them. This is a bit
181 * another. However in order to keep self refresh entirely hidden from
184 * At the end, we queue up the self refresh entry work so we can enter PSR after
227 * drm_self_refresh_helper_init - Initializes self refresh helpers for a crtc
228 * @crtc: the crtc which supports self refresh supported displays
265 * drm_self_refresh_helper_cleanup - Cleans up self refresh helpers for a crtc
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/ |
| D | ali_drw.json | 171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
227 "BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
234 "BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
241 "BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
248 "BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
255 "BriefDescription": "An auto-refresh(REF) command to DRAM.",
262 "BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 27 * framework to implement panel self refresh (SR) support. Drivers are
32 * (meaning it knows how to initiate self refresh on the panel).
140 * update the average entry/exit self refresh times on self refresh transitions.
142 * entering self refresh mode after activity.
179 * incompatible with self refresh exit and changes them. This is a bit
181 * another. However in order to keep self refresh entirely hidden from
184 * At the end, we queue up the self refresh entry work so we can enter PSR after
227 * drm_self_refresh_helper_init - Initializes self refresh helpers for a crtc
228 * @crtc: the crtc which supports self refresh supported displays
265 * drm_self_refresh_helper_cleanup - Cleans up self refresh helpers for a crtc
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | sleep.S | 54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
107 @ as possible to eliminate messing about with the refresh clock
159 @ external accesses after SDRAM is put in self-refresh mode
160 @ (see Errata 38 ...hangs when entering self-refresh mode)
165 @ put SDRAM into self-refresh
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| /kernel/linux/linux-6.6/arch/arm/mach-pxa/ |
| D | sleep.S | 55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
108 @ as possible to eliminate messing about with the refresh clock
160 @ external accesses after SDRAM is put in self-refresh mode
161 @ (see Errata 38 ...hangs when entering self-refresh mode)
166 @ put SDRAM into self-refresh
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| /kernel/linux/linux-5.10/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
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| /kernel/linux/linux-6.6/arch/arm/mach-socfpga/ |
| D | self-refresh.S | 44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
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| /kernel/linux/linux-5.10/include/soc/at91/ |
| D | at91sam9_sdramc.h | 26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
27 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
54 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
62 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
63 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
74 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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| /kernel/linux/linux-6.6/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-kfr2r09/ |
| D | sdram.S | 3 * KFR2R09 sdram self/auto-refresh setup code
15 /* code to enter and leave self-refresh. must be self-contained.
21 /* DBSC: put memory in self-refresh mode */
37 /* DBSC: put memory in auto-refresh mode */
55 /* DBSC: re-initialize and put in auto-refresh */
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| /kernel/linux/linux-6.6/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /kernel/linux/linux-5.10/drivers/cpuidle/ |
| D | cpuidle-zynq.c | 9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order
12 * #2 wait-for-interrupt and RAM self refresh
28 /* Add code for DDR self refresh start */ in zynq_enter_idle()
44 .desc = "WFI and RAM Self Refresh",
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| /kernel/linux/linux-5.10/Documentation/fb/ |
| D | modedb.rst | 23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
30 <bpp> and <refresh>, if specified) the timings will be calculated using
81 and coordinated set of standard formats, display refresh rates, and
92 pixelclock, the horizontal sync frequency, or the vertical refresh rate.
127 - acceptable refresh rates are 50, 60, 70 or 85 Hz only
128 - if reduced blanking, the refresh rate must be at 60Hz
152 video=<driver>:<xres>x<yres>[-<bpp>][@refresh]
|