Home
last modified time | relevance | path

Searched +full:reg +full:- +full:offset (Results 1 – 25 of 1096) sorted by relevance

12345678910>>...44

/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000/
De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000/
De1000_osdep.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
22 #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \ argument
23 (iowrite16_rep(base + offset, data, count))
25 #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \ argument
26 (ioread16_rep(base + (offset << 1), data, count))
28 #define er32(reg) \ argument
29 (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
30 ? E1000_##reg : E1000_82542_##reg)))
32 #define ew32(reg, value) \ argument
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/mscc/
Docelot_vsc7514.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
21 #define IFH_EXTRACT_BITFIELD64(x, o, w) (((x) >> (o)) & GENMASK_ULL((w) - 1, 0))
24 REG(ANA_ADVLEARN, 0x009000),
25 REG(ANA_VLANMASK, 0x009004),
26 REG(ANA_PORT_B_DOMAIN, 0x009008),
27 REG(ANA_ANAGEFIL, 0x00900c),
28 REG(ANA_ANEVENTS, 0x009010),
29 REG(ANA_STORMLIMIT_BURST, 0x009014),
30 REG(ANA_STORMLIMIT_CFG, 0x009018),
31 REG(ANA_ISOLATED_PORTS, 0x009028),
[all …]
/kernel/linux/linux-5.10/drivers/net/dsa/ocelot/
Dseville_vsc9953.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/pcs-lynx.h>
23 REG(ANA_ADVLEARN, 0x00b500),
24 REG(ANA_VLANMASK, 0x00b504),
26 REG(ANA_ANAGEFIL, 0x00b50c),
27 REG(ANA_ANEVENTS, 0x00b510),
28 REG(ANA_STORMLIMIT_BURST, 0x00b514),
29 REG(ANA_STORMLIMIT_CFG, 0x00b518),
30 REG(ANA_ISOLATED_PORTS, 0x00b528),
31 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
[all …]
Dfelix_vsc9959.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2018-2019 NXP Semiconductors
12 #include <linux/pcs-lynx.h>
22 REG(ANA_ADVLEARN, 0x0089a0),
23 REG(ANA_VLANMASK, 0x0089a4),
25 REG(ANA_ANAGEFIL, 0x0089ac),
26 REG(ANA_ANEVENTS, 0x0089b0),
27 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
28 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
29 REG(ANA_ISOLATED_PORTS, 0x0089c8),
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_translate_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_translate_dce120.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_translate_dcn10.c2 * Copyright 2013-15 Advanced Micro Devices, Inc.
27 * Pre-requisites: headers required by header of this unit
51 #define REG(reg_name)\ macro
62 uint32_t offset, in offset_to_id() argument
67 switch (offset) { in offset_to_id()
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
140 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
27 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
30 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
33 unsigned int reg; in palmas_gpio_get() local
34 int gpio16 = (offset/8); in palmas_gpio_get()
36 offset %= 8; in palmas_gpio_get()
37 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
39 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
41 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
45 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
Dgpio-msic.c1 // SPDX-License-Identifier: GPL-2.0
18 /* the offset for the mapping of global gpio pin to irq */
52 * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
61 static int msic_gpio_to_ireg(unsigned offset) in msic_gpio_to_ireg() argument
63 if (offset >= MSIC_NUM_GPIO) in msic_gpio_to_ireg()
64 return -EINVAL; in msic_gpio_to_ireg()
66 if (offset < 8) in msic_gpio_to_ireg()
67 return INTEL_MSIC_GPIO0LV0CTLI - offset; in msic_gpio_to_ireg()
68 if (offset < 16) in msic_gpio_to_ireg()
69 return INTEL_MSIC_GPIO1LV0CTLI - offset + 8; in msic_gpio_to_ireg()
[all …]
Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
52 * @offset: the EIC controller's offset address of the PMIC.
53 * @reg: the array to cache the EIC registers.
61 u32 offset; member
62 u8 reg[CACHE_NR_REGS]; member
67 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
68 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
71 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-palmas.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static int palmas_gpio_get(struct gpio_chip *gc, unsigned offset) in palmas_gpio_get() argument
29 struct palmas *palmas = pg->palmas; in palmas_gpio_get()
32 unsigned int reg; in palmas_gpio_get() local
33 int gpio16 = (offset/8); in palmas_gpio_get()
35 offset %= 8; in palmas_gpio_get()
36 reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; in palmas_gpio_get()
38 ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); in palmas_gpio_get()
40 dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); in palmas_gpio_get()
44 if (val & BIT(offset)) in palmas_gpio_get()
[all …]
Dgpio-pmic-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48 * struct sprd_pmic_eic - PMIC EIC controller
51 * @offset: the EIC controller's offset address of the PMIC.
52 * @reg: the array to cache the EIC registers.
59 u32 offset; member
60 u8 reg[CACHE_NR_REGS]; member
65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_pmic_eic_update() argument
66 u16 reg, unsigned int val) in sprd_pmic_eic_update() argument
69 u32 shift = SPRD_PMIC_EIC_BIT(offset); in sprd_pmic_eic_update()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_translate_dcn30.c27 * Pre-requisites: headers required by header of this unit
60 #undef REG
61 #define REG(reg_name)\ macro
72 uint32_t offset, in offset_to_id() argument
77 switch (offset) { in offset_to_id()
79 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
109 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
136 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_translate_dcn20.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_translate_dcn30.c27 * Pre-requisites: headers required by header of this unit
59 #undef REG
60 #define REG(reg_name)\ macro
71 uint32_t offset, in offset_to_id() argument
76 switch (offset) { in offset_to_id()
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
134 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_translate_dcn20.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
56 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 uint32_t offset, in offset_to_id() argument
71 switch (offset) { in offset_to_id()
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
Dhw_translate_dcn32.c27 * Pre-requisites: headers required by header of this unit
52 #undef REG
53 #define REG(reg_name)\ macro
54 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
64 uint32_t offset, in offset_to_id() argument
69 switch (offset) { in offset_to_id()
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
121 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_translate_dcn21.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
65 uint32_t offset, in offset_to_id() argument
70 switch (offset) { in offset_to_id()
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
106 case REG(DC_GPIO_HPD_A): in offset_to_id()
132 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
133 case REG(DC_GPIO_GENLK_A): in offset_to_id()
157 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_translate_dcn21.c27 * Pre-requisites: headers required by header of this unit
54 #undef REG
55 #define REG(reg_name)\ macro
65 uint32_t offset, in offset_to_id() argument
70 switch (offset) { in offset_to_id()
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
106 case REG(DC_GPIO_HPD_A): in offset_to_id()
132 /* REG(DC_GPIO_GENLK_MASK */ in offset_to_id()
133 case REG(DC_GPIO_GENLK_A): in offset_to_id()
158 case REG(DC_GPIO_DDC1_A): in offset_to_id()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c36 #define REG(reg)\ macro
37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
130 dpp2_program_degamma_lut(dpp_base, params->rgb_resulted, params->hw_points_num, !is_ram_a); in dpp2_set_degamma_pwl()
183 /* value stored in dbg reg will be 1 greater than mode we want */ in program_gamut_remap()
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
[all …]
/kernel/linux/linux-6.6/io_uring/
Dtctx.c1 // SPDX-License-Identifier: GPL-2.0
22 mutex_lock(&ctx->uring_lock); in io_init_wq_offload()
23 hash = ctx->hash_map; in io_init_wq_offload()
27 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
28 return ERR_PTR(-ENOMEM); in io_init_wq_offload()
30 refcount_set(&hash->refs, 1); in io_init_wq_offload()
31 init_waitqueue_head(&hash->wait); in io_init_wq_offload()
32 ctx->hash_map = hash; in io_init_wq_offload()
34 mutex_unlock(&ctx->uring_lock); in io_init_wq_offload()
42 concurrency = min(ctx->sq_entries, 4 * num_online_cpus()); in io_init_wq_offload()
[all …]

12345678910>>...44