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/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
Dclk-busy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
16 static int clk_busy_wait(void __iomem *reg, u8 shift) in clk_busy_wait() argument
20 while (readl_relaxed(reg) & (1 << shift)) in clk_busy_wait()
22 return -ETIMEDOUT; in clk_busy_wait()
30 void __iomem *reg; member
31 u8 shift; member
46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); in clk_busy_divider_recalc_rate()
54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); in clk_busy_divider_round_rate()
63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ argument
72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
78 #define imx_clk_pfd(name, parent_name, reg, idx) \ argument
79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
90 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra30-mc.h>
44 .reg = 0x228,
48 .reg = 0x2e8,
49 .shift = 0,
58 .reg = 0x228,
62 .reg = 0x2f4,
63 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2e8,
[all …]
Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
[all …]
Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
34 .reg = 0x228,
38 .reg = 0x2f4,
39 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2e8,
[all …]
Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra124-mc.h>
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
51 .reg = 0x228,
55 .reg = 0x2e8,
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
18 reg = <0x0d40>;
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,omap3-interface-clock";
20 ti,bit-shift = <3>;
21 reg = <0x0a14>;
25 #clock-cells = <0>;
[all …]
Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
24 ti,bit-shift = <8>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
13 reg = <0x78>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
27 reg = <0x78>;
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra114.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/memory/tegra114-mc.h>
20 .reg = 0x34c,
21 .shift = 0,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
48 .reg = 0x228,
52 .reg = 0x2f4,
53 .shift = 0,
[all …]
Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra210-mc.h>
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
37 .reg = 0x228,
41 .reg = 0x2f4,
42 .shift = 0,
53 .reg = 0x228,
57 .reg = 0x2e8,
[all …]
Dtegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra124-mc.h>
21 .reg = 0x34c,
22 .shift = 0,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
49 .reg = 0x228,
53 .reg = 0x2f4,
54 .shift = 0,
[all …]
Dtegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/memory/tegra30-mc.h>
42 .reg = 0x34c,
43 .shift = 0,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
72 .reg = 0x228,
76 .reg = 0x2f4,
77 .shift = 0,
[all …]
/kernel/linux/linux-6.6/drivers/bus/
Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
[all …]
/kernel/linux/linux-5.10/drivers/bus/
Dda8xx-mstpri.c1 // SPDX-License-Identifier: GPL-2.0-only
24 * some changes (as is the case for the LCD controller on da850-lcdk - the
54 int reg; member
55 int shift; member
61 .reg = DA8XX_MSTPRI0_OFFSET,
62 .shift = 0,
66 .reg = DA8XX_MSTPRI0_OFFSET,
67 .shift = 4,
71 .reg = DA8XX_MSTPRI0_OFFSET,
72 .shift = 16,
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dvp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * struct omap_vp_ops - per-VP operations
36 * struct omap_vp_common - register data common to all VDDs
37 * @vpconfig_erroroffset_mask: ERROROFFSET bitmask in the PRM_VP*_CONFIG reg
38 * @vpconfig_errorgain_mask: ERRORGAIN bitmask in the PRM_VP*_CONFIG reg
39 * @vpconfig_initvoltage_mask: INITVOLTAGE bitmask in the PRM_VP*_CONFIG reg
40 * @vpconfig_timeouten: TIMEOUT bitmask in the PRM_VP*_CONFIG reg
41 * @vpconfig_initvdd: INITVDD bitmask in the PRM_VP*_CONFIG reg
42 * @vpconfig_forceupdate: FORCEUPDATE bitmask in the PRM_VP*_CONFIG reg
43 * @vpconfig_vpenable: VPENABLE bitmask in the PRM_VP*_CONFIG reg
[all …]
/kernel/linux/linux-6.6/drivers/soc/aspeed/
Daspeed-uart-routing.c1 // SPDX-License-Identifier: GPL-2.0+
41 uint8_t reg; member
43 uint8_t shift; member
68 .reg = HICR9,
69 .shift = 8,
88 .reg = HICRA,
89 .shift = 28,
108 .reg = HICRA,
109 .shift = 25,
126 .reg = HICRA,
[all …]
/kernel/linux/linux-6.6/drivers/regulator/
Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
41 int *reg, int *shift) in max8998_get_enable_register() argument
47 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
48 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
51 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
52 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
55 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
[all …]
/kernel/linux/linux-5.10/drivers/regulator/
Dmax8998.c1 // SPDX-License-Identifier: GPL-2.0+
3 // max8998.c - Voltage regulator driver for the Maxim 8998
5 // Copyright (C) 2009-2010 Samsung Electronics
23 #include <linux/mfd/max8998-private.h>
41 int *reg, int *shift) in max8998_get_enable_register() argument
47 *reg = MAX8998_REG_ONOFF1; in max8998_get_enable_register()
48 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
51 *reg = MAX8998_REG_ONOFF2; in max8998_get_enable_register()
52 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
55 *reg = MAX8998_REG_ONOFF3; in max8998_get_enable_register()
[all …]

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