| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 17 debug blocks defined within this memory space.
21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
44 range of the DCSR space.
48 #address-cells = <1>;
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| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
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| D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 reg = <0x320000 0x10000>;
30 There must be a sub-node for each job queue present in RAID Engine
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 17 debug blocks defined within this memory space.
21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
44 range of the DCSR space.
48 #address-cells = <1>;
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| D | dma.txt | 4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
[all …]
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| D | raideng.txt | 3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 reg = <0x320000 0x10000>;
30 There must be a sub-node for each job queue present in RAID Engine
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/ |
| D | cgs_common.h | 32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
93 * cgs_write_register() - Write an MMIO register
102 * cgs_read_ind_register() - Read an indirect register
108 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
112 * cgs_write_ind_register() - Write an indirect register
117 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/ |
| D | cgs_common.h | 32 * enum cgs_ind_reg - Indirect register spaces
45 * enum cgs_ucode_id - Firmware types for different IPs
65 * struct cgs_firmware_info - Firmware information
84 * cgs_read_register() - Read an MMIO register
93 * cgs_write_register() - Write an MMIO register
102 * cgs_read_ind_register() - Read an indirect register
108 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
112 * cgs_write_ind_register() - Write an indirect register
117 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT argument
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| /kernel/linux/linux-6.6/arch/sh/drivers/pci/ |
| D | pci-sh7751.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Support for SH7751 targets
6 * Paul Mundt (lethal@linux-sh.org) (c) 2003
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
27 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
30 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
50 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
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| /kernel/linux/linux-5.10/arch/sh/drivers/pci/ |
| D | pci-sh7751.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Low-Level PCI Support for SH7751 targets
6 * Paul Mundt (lethal@linux-sh.org) (c) 2003
18 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
19 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
20 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
22 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
27 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
30 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
50 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
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| /kernel/linux/linux-6.6/arch/mips/loongson2ef/common/cs5536/ |
| D | cs5536_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * read/write operation to the PCI config space of CS5536
12 * configure space are defined in cs5536_modulename.c respectively,
14 * after this virtulizing, user can access the PCI configure space
15 * directly as a normal multi-function PCI device which follows
16 * the PCI-2.2 spec.
24 CS5536_FUNC_START = -1,
53 * write to PCI config space and transfer it to MSR write.
55 void cs5536_pci_conf_write4(int function, int reg, u32 value) in cs5536_pci_conf_write4() argument
59 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) in cs5536_pci_conf_write4()
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| /kernel/linux/linux-5.10/arch/mips/loongson2ef/common/cs5536/ |
| D | cs5536_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * read/write operation to the PCI config space of CS5536
12 * configure space are defined in cs5536_modulename.c respectively,
14 * after this virtulizing, user can access the PCI configure space
15 * directly as a normal multi-function PCI device which follows
16 * the PCI-2.2 spec.
24 CS5536_FUNC_START = -1,
53 * write to PCI config space and transfer it to MSR write.
55 void cs5536_pci_conf_write4(int function, int reg, u32 value) in cs5536_pci_conf_write4() argument
59 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) in cs5536_pci_conf_write4()
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| /kernel/linux/linux-6.6/drivers/pci/ |
| D | pci-bridge-emul.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* PCI configuration space of a PCI-to-PCI bridge. */
42 /* PCI configuration space of the PCIe capabilities */
78 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
82 * in-memory copy of the configuration space.
85 int reg, u32 *value);
88 * Same as ->read_base(), except it is for reading from the
89 * PCIe capability configuration space.
92 int reg, u32 *value);
95 * Same as ->read_base(), except it is for reading from the
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | designware-pcie.txt | 4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
8 address space. For designware core version >= 4.80, contains
9 the configuration and ATU address space
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
11 the ATU address space.
12 (The old way of getting the configuration address space from "ranges"
15 - #address-cells: set to <3>
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| /kernel/linux/linux-5.10/arch/arm64/lib/ |
| D | copy_in_user.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copy from user space to user space
10 #include <asm/asm-uaccess.h>
15 * Copy from user space to user space (alignment handled by the hardware)
18 * x0 - to
19 * x1 - from
20 * x2 - n
22 * x0 - bytes not copied
24 .macro ldrb1 reg, ptr, val
25 uao_user_alternative 9998f, ldrb, ldtrb, \reg, \ptr, \val
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
8 - reg: Address and length of the register set for the device. It contains
9 the information of registers in the same order as described by reg-names
10 - reg-names: Should contain the reg names
11 "control_port": MAC configuration space region
12 "tx_csr": xDMA Tx dispatcher control and status space region
13 "tx_desc": MSGDMA Tx dispatcher descriptor space region
14 "rx_csr" : xDMA Rx dispatcher control and status space region
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | io.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * Allows thread-safe access to registers shared by unrelated subsystems.
13 * The access is protected by a single MMIO-wide lock.
15 void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify_relaxed() argument
21 value = readl_relaxed(reg) & ~mask; in atomic_io_modify_relaxed()
23 writel_relaxed(value, reg); in atomic_io_modify_relaxed()
28 void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify() argument
34 value = readl_relaxed(reg) & ~mask; in atomic_io_modify()
36 writel(value, reg); in atomic_io_modify()
42 * Copy data from IO memory space to "real" memory space.
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | io.c | 1 // SPDX-License-Identifier: GPL-2.0
12 * Allows thread-safe access to registers shared by unrelated subsystems.
13 * The access is protected by a single MMIO-wide lock.
15 void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify_relaxed() argument
21 value = readl_relaxed(reg) & ~mask; in atomic_io_modify_relaxed()
23 writel_relaxed(value, reg); in atomic_io_modify_relaxed()
28 void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) in atomic_io_modify() argument
34 value = readl_relaxed(reg) & ~mask; in atomic_io_modify()
36 writel(value, reg); in atomic_io_modify()
42 * Copy data from IO memory space to "real" memory space.
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| /kernel/linux/linux-6.6/arch/arm64/include/asm/ |
| D | kvm_mmu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
26 * runtime VA space, at the same time.
28 * Given that the kernel uses VA_BITS for its entire address space,
29 * and that half of that space (VA_BITS - 1) is used for the linear
30 * mapping, we can also limit the EL2 space to (VA_BITS - 1).
32 * The main question is "Within the VA_BITS space, does EL2 use the
33 * top or the bottom half of that space to shadow the kernel's linear
41 * if (T & BIT(VA_BITS - 1))
44 * HYP_VA_MIN = 1 << (VA_BITS - 1)
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| /kernel/linux/linux-5.10/arch/mips/include/asm/ |
| D | uaccess.h | 16 #include <asm/asm-eva.h>
58 * userspace address. Note that we limit 32-bit userspace to 0x7fff8000 but
60 * we use 0x80000000 here on 32-bit kernels. If a process passes an invalid
61 * address in this range it's the process's problem, not ours :-)
72 #define get_fs() (current_thread_info()->addr_limit)
73 #define set_fs(x) (current_thread_info()->addr_limit = (x))
78 * eva_kernel_access() - determine whether kernel memory access on an EVA system
98 * - "addr" doesn't have any high-bits set
99 * - AND "size" doesn't have any high-bits set
100 * - AND "addr+size" doesn't have any high-bits set
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| /kernel/linux/linux-5.10/drivers/pci/ |
| D | pci-bridge-emul.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* PCI configuration space of a PCI-to-PCI bridge. */
42 /* PCI configuration space of the PCIe capabilities */
78 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
82 * in-memory copy of the configuration space.
85 int reg, u32 *value);
88 * Same as ->read_base(), except it is for reading from the
89 * PCIe capability configuration space.
92 int reg, u32 *value);
95 * space. old is the current value, new is the new value being
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
14 4th - Soc efuse register address space.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
4 APM X-Gene SoC.
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
9 - reg: Address and length of the register set for the device.
11 1st - DMA control and status register address space.
12 2nd - Descriptor ring control and status register address space.
13 3rd - Descriptor ring command register address space.
14 4th - Soc efuse register address space.
[all …]
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