Home
last modified time | relevance | path

Searched full:reg (Results 1 – 25 of 421) sorted by relevance

12345678910>>...17

/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
Dtarget.h56 static inline vixl::aarch64::Register VixlRegCaseScalar(Reg reg) in VixlRegCaseScalar() argument
58 size_t regSize = reg.GetSize(); in VixlRegCaseScalar()
65 auto vixlReg = vixl::aarch64::Register(reg.GetId(), regSize); in VixlRegCaseScalar()
70 static inline vixl::aarch64::Register VixlReg(Reg reg) in VixlReg() argument
72 ASSERT(reg.IsValid()); in VixlReg()
73 if (reg.IsScalar()) { in VixlReg()
74 return VixlRegCaseScalar(reg); in VixlReg()
76 if (reg.GetId() == vixl::aarch64::sp.GetCode()) { in VixlReg()
85 static inline vixl::aarch64::Register VixlRegCaseScalar(Reg reg, const uint8_t size) in VixlRegCaseScalar() argument
87 auto vixlReg = vixl::aarch64::Register(reg.GetId(), (size < WORD_SIZE ? WORD_SIZE : size)); in VixlRegCaseScalar()
[all …]
Dregfile.cpp31 bool Aarch64RegisterDescription::IsRegUsed(ArenaVector<Reg> vecReg, Reg reg) in IsRegUsed() argument
33 …auto equality = [reg](Reg in) { return (reg.GetId() == in.GetId()) && (reg.GetType() == in.GetType… in IsRegUsed()
37 ArenaVector<Reg> Aarch64RegisterDescription::GetCalleeSaved() in GetCalleeSaved()
39 ArenaVector<Reg> out(GetAllocator()->Adapter()); in GetCalleeSaved()
42 out.emplace_back(Reg(i, FLOAT64_TYPE)); in GetCalleeSaved()
48 out.emplace_back(Reg(i, INT64_TYPE)); in GetCalleeSaved()
54 void Aarch64RegisterDescription::SetCalleeSaved(const ArenaVector<Reg> &regs) in SetCalleeSaved()
60 bool vectorUsed = IsRegUsed(regs, Reg(i, FLOAT64_TYPE)); in SetCalleeSaved()
66 bool scalarUsed = IsRegUsed(regs, Reg(i, INT64_TYPE)); in SetCalleeSaved()
83 void Aarch64RegisterDescription::SetUsedRegs(const ArenaVector<Reg> &regs) in SetUsedRegs()
[all …]
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/
Dencode.h141 virtual void Encode##opc(Reg, Reg) \
149 virtual void Encode##opc(Reg, Reg, Reg) \
153 virtual void Encode##opc(Reg, Reg, Imm) \
161 virtual void Encode##opc(Reg, Reg, Shift) \
179 …virtual void EncodeAddOverflow(LabelHolder::LabelId id, Reg dst, Reg src0, Reg src1, Condition cc);
180 …virtual void EncodeSubOverflow(LabelHolder::LabelId id, Reg dst, Reg src0, Reg src1, Condition cc);
181 …virtual void EncodeMulOverflow(LabelHolder::LabelId id, Reg dst, Reg src0, Reg src1, Condition cc);
182 virtual void EncodeNegOverflowAndZero(LabelHolder::LabelId id, Reg dst, Reg src);
183 virtual void EncodeFastPathDynamicCast(Reg dst, Reg src, LabelHolder::LabelId slow);
184 virtual void EncodeJsDoubleToCharCast(Reg dst, Reg src);
[all …]
Dencode.cpp74 …er::EncodeAddOverflow([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] Reg dst, in EncodeAddOverflow()
75 … [[maybe_unused]] Reg src0, [[maybe_unused]] Reg src1, [[maybe_unused]] Condition cc) in EncodeAddOverflow()
80 …er::EncodeSubOverflow([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] Reg dst, in EncodeSubOverflow()
81 … [[maybe_unused]] Reg src0, [[maybe_unused]] Reg src1, [[maybe_unused]] Condition cc) in EncodeSubOverflow()
86 …er::EncodeMulOverflow([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] Reg dst, in EncodeMulOverflow()
87 … [[maybe_unused]] Reg src0, [[maybe_unused]] Reg src1, [[maybe_unused]] Condition cc) in EncodeMulOverflow()
92 …odeNegOverflowAndZero([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] Reg dst, in EncodeNegOverflowAndZero()
93 [[maybe_unused]] Reg src) in EncodeNegOverflowAndZero()
98 void Encoder::EncodeFastPathDynamicCast([[maybe_unused]] Reg dst, [[maybe_unused]] Reg src, in EncodeFastPathDynamicCast()
104 void Encoder::EncodeJsDoubleToCharCast([[maybe_unused]] Reg dst, [[maybe_unused]] Reg src) in EncodeJsDoubleToCharCast()
[all …]
Dtarget_info.h27 // caller reg mask: 0000111111000111 and
28 // callee reg mask: 1111000000001000
50 #define DEFINE_NUMERIC_REGISTERS(REG) \ argument
51 REG(0) \
52 REG(1) \
53 REG(2) \
54 REG(3) \
55 REG(4) \
56 REG(5) \
57 REG(6) \
[all …]
Dslow_path.h155 void SetTmpReg(Reg reg) in SetTmpReg() argument
157 tmpReg_ = reg; in SetTmpReg()
159 Reg GetTmpReg() const in GetTmpReg()
165 Reg tmpReg_ {INVALID_REGISTER};
174 void SetDstReg(Reg reg) in SetDstReg() argument
176 dstReg_ = reg; in SetDstReg()
179 void SetAddrReg(Reg reg) in SetAddrReg() argument
181 addrReg_ = reg; in SetAddrReg()
195 Reg dstReg_ {INVALID_REGISTER};
196 Reg addrReg_ {INVALID_REGISTER};
[all …]
Dregisters_description.h33 // caller reg mask: 0000111111000111 and
34 // callee reg mask: 1111000000001000
57 virtual ArenaVector<Reg> GetCalleeSaved() = 0;
58 virtual void SetCalleeSaved(const ArenaVector<Reg> &) = 0;
60 virtual void SetUsedRegs(const ArenaVector<Reg> &) = 0;
62 virtual Reg GetZeroReg() const = 0;
63 virtual bool IsZeroReg(Reg reg) const = 0;
64 virtual Reg::RegIDType GetTempReg() = 0;
65 virtual Reg::RegIDType GetTempVReg() = 0;
74 virtual bool IsCalleeRegister(Reg reg) = 0;
[all …]
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/
Dtarget.h132 * | AMD64 Reg | Panda Reg |
150 * | <no reg> | r16-r31 |
163 ArenaVector<Reg> GetCalleeSaved() override;
164 void SetCalleeSaved(const ArenaVector<Reg> &regs) override;
166 void SetUsedRegs(const ArenaVector<Reg> &regs) override;
170 bool IsCalleeRegister(Reg reg) override;
171 Reg GetZeroReg() const override;
172 bool IsZeroReg([[maybe_unused]] Reg reg) const override;
173 Reg::RegIDType GetTempReg() override;
174 Reg::RegIDType GetTempVReg() override;
[all …]
Dregfile.cpp31 bool Amd64RegisterDescription::IsRegUsed(ArenaVector<Reg> vecReg, Reg reg) in IsRegUsed() argument
33 …auto equality = [reg](Reg in) { return (reg.GetId() == in.GetId()) && (reg.GetType() == in.GetType… in IsRegUsed()
37 ArenaVector<Reg> Amd64RegisterDescription::GetCalleeSaved() in GetCalleeSaved()
39 ArenaVector<Reg> out(GetAllocator()->Adapter()); in GetCalleeSaved()
42 out.emplace_back(Reg(i, INT64_TYPE)); in GetCalleeSaved()
45 out.emplace_back(Reg(i, FLOAT64_TYPE)); in GetCalleeSaved()
51 void Amd64RegisterDescription::SetCalleeSaved(const ArenaVector<Reg> &regs) in SetCalleeSaved()
57 bool scalarUsed = IsRegUsed(regs, Reg(i, INT64_TYPE)); in SetCalleeSaved()
63 bool vectorUsed = IsRegUsed(regs, Reg(i, FLOAT64_TYPE)); in SetCalleeSaved()
74 void Amd64RegisterDescription::SetUsedRegs(const ArenaVector<Reg> &regs) in SetUsedRegs()
[all …]
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/
Dtarget.h48 static inline vixl::aarch32::Register VixlReg(Reg reg) in VixlReg() argument
50 ASSERT(reg.IsValid()); in VixlReg()
51 if (reg.IsScalar()) { in VixlReg()
52 auto vixlReg = vixl::aarch32::Register(reg.GetId()); in VixlReg()
62 static inline vixl::aarch32::Register VixlRegU(Reg reg) in VixlRegU() argument
64 ASSERT(reg.IsValid()); in VixlRegU()
65 if (reg.IsScalar()) { in VixlRegU()
66 auto vixlReg = vixl::aarch32::Register(reg.GetId() + 1); in VixlRegU()
67 ASSERT(reg.GetId() <= AVAILABLE_DOUBLE_WORD_REGISTERS * 2U); in VixlRegU()
75 static inline vixl::aarch32::VRegister VixlVRegCaseWordSize(Reg reg) in VixlVRegCaseWordSize() argument
[all …]
Dregfile.cpp42 aarch32RegList_.emplace_back(Reg(i, INT32_TYPE)); in Aarch32RegisterDescription()
43 aarch32RegList_.emplace_back(Reg(i, FLOAT32_TYPE)); in Aarch32RegisterDescription()
56 bool Aarch32RegisterDescription::IsRegUsed(ArenaVector<Reg> vecReg, Reg reg) in IsRegUsed() argument
58 …auto equality = [reg](Reg in) { return (reg.GetId() == in.GetId()) && (reg.GetType() == in.GetType… in IsRegUsed()
63 bool Aarch32RegisterDescription::IsTmp(Reg reg) in IsTmp() argument
65 if (reg.IsScalar()) { in IsTmp()
67 if (it == reg.GetId()) { in IsTmp()
73 ASSERT(reg.IsFloat()); in IsTmp()
75 if (it == reg.GetId()) { in IsTmp()
82 // Reg Mask
[all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/
Dassembler.h178 virtual void Mov(InsnSize insnSize, Reg srcReg, Reg destReg) = 0;
179 virtual void Mov(InsnSize insnSize, const ImmOpnd &immOpnd, Reg reg) = 0;
180 virtual void Mov(InsnSize insnSize, const Mem &mem, Reg reg) = 0;
181 virtual void Mov(InsnSize insnSize, Reg reg, const Mem &mem) = 0;
184 virtual void Mov(Reg srcReg, Reg destReg, bool isMovD = true) = 0;
185 virtual void MovF(const Mem &mem, Reg reg, bool isSingle = true) = 0;
186 virtual void MovF(Reg reg, const Mem &mem, bool isSingle = true) = 0;
188 virtual void Movabs(const ImmOpnd &immOpnd, Reg reg) = 0;
189 virtual void Movabs(int64 symIdx, Reg reg) = 0;
191 virtual void Push(InsnSize insnSize, Reg reg) = 0;
[all …]
Dasm_assembler.h165 void Mov(InsnSize insnSize, Reg srcReg, Reg destReg) override;
166 void Mov(InsnSize insnSize, const ImmOpnd &immOpnd, Reg reg) override;
167 void Mov(InsnSize insnSize, const Mem &mem, Reg reg) override;
168 void Mov(InsnSize insnSize, Reg reg, const Mem &mem) override;
171 void Mov(Reg srcReg, Reg destReg, bool isMovD) override;
172 void MovF(const Mem &mem, Reg reg, bool isSingle) override;
173 void MovF(Reg reg, const Mem &mem, bool isSingle) override;
175 void Movabs(const ImmOpnd &immOpnd, Reg reg) override;
176 void Movabs(int64 symIdx, Reg reg) override;
178 void Push(InsnSize insnSize, Reg reg) override;
[all …]
Delf_assembler.h156 void Mov(InsnSize insnSize, Reg srcReg, Reg destReg) override;
157 void Mov(InsnSize insnSize, const ImmOpnd &immOpnd, Reg reg) override;
158 void Mov(InsnSize insnSize, const Mem &mem, Reg reg) override;
159 void Mov(InsnSize insnSize, Reg reg, const Mem &mem) override;
162 void Mov(Reg srcReg, Reg destReg, bool isMovD) override;
163 void MovF(const Mem &mem, Reg reg, bool isSingle) override;
164 void MovF(Reg reg, const Mem &mem, bool isSingle) override;
166 void Movabs(const ImmOpnd &immOpnd, Reg reg) override;
167 void Movabs(int64 symIdx, Reg reg) override;
169 void Push(InsnSize insnSize, Reg reg) override;
[all …]
/arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/
Dreg_map.cpp25 for (size_t reg = priority_reg; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
26 if (!reg_mask.IsSet(reg)) { in SetMask()
27 codegen_reg_map_.push_back(reg); in SetMask()
33 for (size_t reg = 0; reg < priority_reg; ++reg) { in SetMask() local
34 if (!reg_mask.IsSet(reg)) { in SetMask()
35 codegen_reg_map_.push_back(reg); in SetMask()
41 for (size_t reg = 0; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
42 if (reg_mask.IsSet(reg)) { in SetMask()
43 codegen_reg_map_.push_back(reg); in SetMask()
53 for (size_t reg = 0; reg < first_callee_reg; ++reg) { in SetCallerFirstMask() local
[all …]
/arkcompiler/runtime_core/compiler/tests/aarch32/
Dcallconv32_test.cpp98 // std::variant<Reg, uint8_t> GetNativeParam(const TypeInfo& type) in TEST_F()
105 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
106 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
107 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in TEST_F()
111 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
112 EXPECT_EQ(std::get<Reg>(ret).GetId(), i); in TEST_F()
113 EXPECT_EQ(std::get<Reg>(ret), Reg(i, INT8_TYPE)); in TEST_F()
121 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
122 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
123 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in TEST_F()
[all …]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/
Dasm_assembler.cpp568 void AsmAssembler::Mov(InsnSize insnSize, Reg srcReg, Reg destReg) in Mov()
577 void AsmAssembler::Mov(InsnSize insnSize, const ImmOpnd &immOpnd, Reg reg) in Mov() argument
582 EmitImmOrSymbolReg(immOpnd.first, immOpnd.second, reg); in Mov()
586 void AsmAssembler::Mov(InsnSize insnSize, const Mem &mem, Reg reg) in Mov() argument
591 EmitMemReg(mem, reg); in Mov()
595 void AsmAssembler::Mov(InsnSize insnSize, Reg reg, const Mem &mem) in Mov() argument
600 EmitRegMem(reg, mem); in Mov()
614 void AsmAssembler::Mov(Reg srcReg, Reg destReg, bool isMovD) in Mov()
625 void AsmAssembler::MovF(const Mem &mem, Reg reg, bool isSingle) in MovF() argument
632 EmitMemReg(mem, reg); in MovF()
[all …]
Delf_assembler.cpp320 void ElfAssembler::OpReg(Reg reg, uint8 opCode1, uint8 opCode2, uint8 modReg) in OpReg() argument
322 if (HasOpndSizePrefix(reg)) { in OpReg()
325 uint8 rex = GetRex(reg); in OpReg()
329 Encodeb(opCode1 | (GetRegSize(reg) == k8Bits ? 0 : 1)); in OpReg()
333 uint8 modrm = GetRegCodeId(reg); in OpReg()
334 SetModRM(GetMod(reg), modReg, modrm); in OpReg()
397 void ElfAssembler::OpRR(Reg reg1, Reg reg2, uint8 opCode1, uint8 opCode2, bool extInsn) in OpRR()
416 void ElfAssembler::OpRM(Reg reg, const Mem &mem, uint8 opCode1, uint8 opCode2, bool extInsn) in OpRM() argument
418 if (!extInsn && HasOpndSizePrefix(reg)) { in OpRM()
424 uint8 rex = GetRex(mem, reg); in OpRM()
[all …]
/arkcompiler/runtime_core/static_core/compiler/tests/aarch32/
Dcallconv32_test.cpp89 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in CheckMissesDueAlign()
90 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in CheckMissesDueAlign()
91 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in CheckMissesDueAlign()
94 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in CheckMissesDueAlign()
95 EXPECT_EQ(std::get<Reg>(ret).GetId(), 2U); in CheckMissesDueAlign()
96 EXPECT_EQ(std::get<Reg>(ret), Reg(2U, INT64_TYPE)); in CheckMissesDueAlign()
130 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in CheckMixHfloatSfloat1()
131 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in CheckMixHfloatSfloat1()
132 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in CheckMixHfloatSfloat1()
135 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in CheckMixHfloatSfloat1()
[all …]
/arkcompiler/runtime_core/static_core/compiler/optimizer/optimizations/regalloc/
Dreg_map.cpp27 for (size_t reg = priorityReg; reg < maskSize; ++reg) { in SetMask() local
28 if (!regMask.IsSet(reg)) { in SetMask()
29 codegenRegMap_.push_back(reg); in SetMask()
35 for (size_t reg = 0; reg < priorityReg; ++reg) { in SetMask() local
36 if (!regMask.IsSet(reg)) { in SetMask()
37 codegenRegMap_.push_back(reg); in SetMask()
51 for (size_t reg = 0; reg < firstCalleeReg; ++reg) { in SetCallerFirstMask() local
52 if (!regMask.IsSet(reg)) { in SetCallerFirstMask()
53 codegenRegMap_.push_back(reg); in SetCallerFirstMask()
59 for (size_t reg = lastCalleeReg + 1; reg < maskSize; ++reg) { in SetCallerFirstMask() local
[all …]
/arkcompiler/runtime_core/compiler/tests/aarch64/
Dcallconv64_test.cpp90 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
97 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
98 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
99 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in TEST_F()
103 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
104 EXPECT_EQ(std::get<Reg>(ret).GetId(), i); in TEST_F()
105 EXPECT_EQ(std::get<Reg>(ret), Reg(i, INT8_TYPE)); in TEST_F()
113 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
114 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
115 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in TEST_F()
[all …]
/arkcompiler/runtime_core/static_core/compiler/tests/aarch64/
Dcallconv64_test.cpp86 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
93 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
94 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
95 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in TEST_F()
99 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
100 EXPECT_EQ(std::get<Reg>(ret).GetId(), i); in TEST_F()
101 EXPECT_EQ(std::get<Reg>(ret), Reg(i, INT8_TYPE)); in TEST_F()
109 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
110 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
111 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in TEST_F()
[all …]
/arkcompiler/runtime_core/static_core/compiler/tests/amd64/
Dcallconv64_test.cpp88 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
96 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
97 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
98 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT8_TYPE)); in TEST_F()
102 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
103 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(i)); in TEST_F()
104 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(i), INT8_TYPE)); in TEST_F()
112 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
113 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
114 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT32_TYPE)); in TEST_F()
[all …]
/arkcompiler/runtime_core/compiler/tests/amd64/
Dcallconv64_test.cpp90 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
98 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
99 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
100 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT8_TYPE)); in TEST_F()
104 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
105 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(i)); in TEST_F()
106 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(i), INT8_TYPE)); in TEST_F()
114 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
115 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
116 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT32_TYPE)); in TEST_F()
[all …]
/arkcompiler/runtime_core/static_core/runtime/arch/
Dasm_support.h54 #define CFI_DEF_CFA(reg, offset) .cfi_def_cfa reg, (offset) argument
58 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
60 #define CFI_REL_OFFSET(reg, offset) .cfi_rel_offset reg, (offset) argument
62 #define CFI_OFFSET(reg, offset) .cfi_offset reg, (offset) argument
68 #define CFI_RESTORE(reg) .cfi_restore reg argument
70 #define CFI_REGISTER(reg, old_reg) .cfi_register reg, old_reg argument
79 #define CFI_DEF_CFA(reg, offset) argument
83 #define CFI_DEF_CFA_REGISTER(reg) argument
85 #define CFI_REL_OFFSET(reg, offset) argument
87 #define CFI_OFFSET(reg, offset) argument
[all …]

12345678910>>...17