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/arkcompiler/ets_frontend/es2panda/test/compiler/debugInfo/
Dtest-for-loop-expected.txt16 "regs": [
29 "regs": [
42 "regs": [
55 "regs": [],
67 "regs": [
79 "regs": [],
89 "regs": [
101 "regs": [
113 "regs": [],
125 "regs": [
[all …]
Dtest-local-variable-expected.txt16 "regs": [
29 "regs": [
42 "regs": [
55 "regs": [],
67 "regs": [],
81 "regs": [],
93 "regs": [
105 "regs": [],
117 "regs": [],
129 "regs": [
[all …]
/arkcompiler/runtime_core/static_core/runtime/interpreter/
Dstate.h109 return BytecodeInstruction(arch::regs::GetPc()); in GetInst()
114 arch::regs::SetPc(inst.GetAddress()); in SetInst()
119 return arch::regs::GetFrame(); in GetFrame()
124 arch::regs::SetFrame(frame); in SetFrame()
125 arch::regs::SetMirrorFp( in SetFrame()
131 return arch::regs::GetDispatchTable(); in GetDispatchTable()
136 return arch::regs::SetDispatchTable(dispatchTable); in SetDispatchTable()
141 return arch::regs::GetThread(); in GetThread()
146 arch::regs::SetThread(thread); in SetThread()
153 fpSpill_ = arch::regs::GetFp(); in SaveState()
[all …]
/arkcompiler/runtime_core/static_core/runtime/tests/
Ddebugger_test.cpp86 static void SetVRegs(Frame *frame, std::vector<VRegValue> &regs) in SetVRegs() argument
89 for (size_t i = 0; i < regs.size(); i++) { in SetVRegs()
90 if (regs[i].isRef) { in SetVRegs()
91 frameHandler.GetVReg(i).SetReference(ToPtr(regs[i].value)); in SetVRegs()
93 frameHandler.GetVReg(i).SetPrimitive(static_cast<int64_t>(regs[i].value)); in SetVRegs()
106 static void CheckFrame(Frame *frame, std::vector<VRegValue> &regs, const MethodInfo &methodInfo) in CheckFrame() argument
108 SetVRegs(frame, regs); in CheckFrame()
127 EXPECT_EQ(debugFrame.GetVReg(i), regs[i].value); in CheckFrame()
128 … EXPECT_EQ(debugFrame.GetVRegKind(i), regs[i].isRef ? tooling::PtFrame::RegisterKind::REFERENCE in CheckFrame()
133 EXPECT_EQ(debugFrame.GetArgument(i), regs[i + nregs].value); in CheckFrame()
[all …]
/arkcompiler/ets_frontend/es2panda/compiler/core/
DregAllocator.cpp76 std::array<VReg *, IRNode::MAX_REG_OPERAND> regs {}; in Run() local
77 auto regCnt = ins->Registers(&regs); in Run()
82 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run()
95 std::array<VReg *, IRNode::MAX_REG_OPERAND> regs {}; in Run() local
96 auto regCnt = ins->Registers(&regs); in Run()
98 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run()
116 throw Error(ErrorType::GENERIC, "Can't adjust spill insns when regs run out"); in AdjustInsRegWhenHasSpill()
124 std::array<VReg *, IRNode::MAX_REG_OPERAND> regs {}; in AdjustInsRegWhenHasSpill() local
125 auto regCnt = ins->Registers(&regs); in AdjustInsRegWhenHasSpill()
131 auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in AdjustInsRegWhenHasSpill()
/arkcompiler/runtime_core/abc2program/common/
Dabc_inst_convert.cpp.erb26 std::vector<uint16_t> regs;
55 regs.push_back(bc_ins.GetVReg(<%=reg_count%>));
86 overhead = regs.size() - pda.GetNumArgs();
88 overhead = regs.size() - pda.GetNumArgs() - 1;
90 if (overhead < 0 || overhead > static_cast<int>(regs.size())) {
91 auto *ins = pandasm::Ins::CreateIns(opcode, regs, imms, ids);
103 regs.pop_back();
107 return pandasm::Ins::CreateIns(opcode, regs, imms, ids);
/arkcompiler/runtime_core/disassembler/templates/
Dbc_ins_to_pandasm_ins.cpp.erb23 std::vector<uint16_t> regs;
52 regs.push_back(bc_ins.GetVReg(<%=reg_count%>));
83 overhead = regs.size() - pda.GetNumArgs();
85 overhead = regs.size() - pda.GetNumArgs() - 1;
87 if (overhead < 0 || overhead > static_cast<int>(regs.size())) {
88 auto *ins = pandasm::Ins::CreateIns(opcode, regs, imms, ids);
100 regs.pop_back();
104 return pandasm::Ins::CreateIns(opcode, regs, imms, ids);
/arkcompiler/runtime_core/static_core/compiler/tests/aarch64/
Dregister64_test.cpp64 std::vector<Reg> regs; in TEST_F() local
66 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
70 for (auto reg : regs) { in TEST_F()
75 regs.clear(); in TEST_F()
77 regs.push_back(encoder.AcquireScratchRegister(floatType)); in TEST_F()
82 for (auto reg : regs) { in TEST_F()
/arkcompiler/runtime_core/static_core/compiler/tests/aarch32/
Dregister32_test.cpp67 std::vector<Reg> regs; in TEST_F() local
69 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
73 for (auto reg : regs) { in TEST_F()
78 regs.clear(); in TEST_F()
80 regs.push_back(encoder.AcquireScratchRegister(floatType)); in TEST_F()
85 for (auto reg : regs) { in TEST_F()
/arkcompiler/runtime_core/compiler/tests/amd64/
Dregister64_test.cpp70 std::vector<Reg> regs; in TEST_F() local
72 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
76 for (auto reg : regs) { in TEST_F()
81 regs.clear(); in TEST_F()
83 regs.push_back(encoder.AcquireScratchRegister(FloatType)); in TEST_F()
88 for (auto reg : regs) { in TEST_F()
/arkcompiler/runtime_core/static_core/compiler/tests/amd64/
Dregister64_test.cpp67 std::vector<Reg> regs; in TEST_F() local
69 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
73 for (auto reg : regs) { in TEST_F()
78 regs.clear(); in TEST_F()
80 regs.push_back(encoder.AcquireScratchRegister(floatType)); in TEST_F()
85 for (auto reg : regs) { in TEST_F()
/arkcompiler/runtime_core/compiler/tests/aarch64/
Dregister64_test.cpp67 std::vector<Reg> regs; in TEST_F() local
69 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
73 for (auto reg : regs) { in TEST_F()
78 regs.clear(); in TEST_F()
80 regs.push_back(encoder.AcquireScratchRegister(FloatType)); in TEST_F()
85 for (auto reg : regs) { in TEST_F()
/arkcompiler/runtime_core/compiler/tests/aarch32/
Dregister32_test.cpp70 std::vector<Reg> regs; in TEST_F() local
72 regs.push_back(encoder.AcquireScratchRegister(INT64_TYPE)); in TEST_F()
76 for (auto reg : regs) { in TEST_F()
81 regs.clear(); in TEST_F()
83 regs.push_back(encoder.AcquireScratchRegister(FloatType)); in TEST_F()
88 for (auto reg : regs) { in TEST_F()
/arkcompiler/ets_frontend/merge_abc/src/
DassemblyInsProto.cpp22 for (const auto &reg : insn->Regs()) { in Serialize()
50 std::vector<uint16_t> regs; in Deserialize() local
51 regs.reserve(protoInsn.regs_size()); in Deserialize()
52 for (const auto &protoReg : protoInsn.regs()) { in Deserialize()
53 regs.push_back(static_cast<uint16_t>(protoReg)); in Deserialize()
82 insn = pandasm::Ins::CreateIns(opcode, regs, imms, ids); in Deserialize()
/arkcompiler/ets_frontend/ets2panda/compiler/templates/
Disa.h.erb49 size_t Registers([[maybe_unused]] std::array<VReg*, MAX_REG_OPERAND>* regs) override
54 size_t Registers([[maybe_unused]] std::array<const VReg*, MAX_REG_OPERAND>* regs) const override
59 size_t OutRegisters([[maybe_unused]] std::array<OutVReg, MAX_REG_OPERAND>* regs) const override
143 size_t Registers([[maybe_unused]] std::array<VReg*, MAX_REG_OPERAND>* regs) override
147 (*regs)[<%= reg_cnt %>] = &<%= reg %>;
153 size_t Registers([[maybe_unused]] std::array<const VReg*, MAX_REG_OPERAND>* regs) const override
157 (*regs)[<%= reg_cnt %>] = &<%= reg %>;
163 size_t OutRegisters([[maybe_unused]] std::array<OutVReg, MAX_REG_OPERAND>* regs) const override
175 (*regs)[<%= reg_cnt %>] = {&<%= reg %>, OperandType::<%= type_to_enum(type) %>};
177 (*regs)[<%= reg_cnt %>] = {nullptr, OperandType::NONE};
[all …]
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/
Dcallconv.cpp119 uint8_t Aarch32CallingConvention::PushRegs(RegMask regs, VRegMask vregs, bool isCallee) in PushRegs() argument
123 if (regs.test(lr)) { in PushRegs()
124 regs.reset(lr); in PushRegs()
127 if (regs.test(fp)) { in PushRegs()
128 regs.reset(fp); in PushRegs()
134 for (size_t i = 0; i < regs.size(); ++i) { in PushRegs()
135 if (regs.test(i)) { in PushRegs()
141 if (((regs.count() + vregs.count()) & 1U) == 1) { in PushRegs()
157 uint8_t Aarch32CallingConvention::PopRegs(RegMask regs, VRegMask vregs, bool isCallee) in PopRegs() argument
162 if (regs.test(fp)) { in PopRegs()
[all …]
/arkcompiler/runtime_core/assembler/templates/
Dins_emit.h.erb47 % def operands(insn, regs = "regs")
55 % ops << "#{regs}[#{nr}]"
102 auto regs = ins->Regs();
144 if (regs.size() < <%= regs_num %>) {
150 if (regs.size() < <%= regs_num %> || imms.size() < <%= imms_num %>) {
154 if (regs.size() < <%= regs_num %>) {
164 auto registers = regs;
Disa.h.erb45 % regs = insn.operands.select(&:reg?)
46 % dst_idx = regs.index(&:dst?) || 'INVALID_REG_IDX'
47 % use_idxs = regs.size.times.select { |idx| regs[idx].src? } || []
/arkcompiler/ets_runtime/ecmascript/platform/unix/ohos/
Dbacktrace.cpp52 static inline ARK_INLINE void GetPcFpRegs([[maybe_unused]] void *regs) in GetPcFpRegs() argument
58 : [base] "+r"(regs) in GetPcFpRegs()
67 uintptr_t regs[2] = {0}; // 2: pc and fp reg in GetPcs() local
68 GetPcFpRegs(regs); in GetPcs()
69 uintptr_t pc = regs[0]; in GetPcs()
70 uintptr_t fp = regs[1]; in GetPcs()
/arkcompiler/ets_frontend/ets2panda/compiler/core/
DregAllocator.cpp148 std::array<VReg *, IRNode::MAX_REG_OPERAND> regs {}; in Run() local
150 const auto regCnt = ins->Registers(&regs); in Run()
152 …Span<VReg *>(regs.data(), regs.data() + (spillMax == std::numeric_limits<int32_t>::max() ? regCnt … in Run()
218 std::array<VReg *, IRNode::MAX_REG_OPERAND> regs {}; in Run() local
220 const auto regCnt = ins->Registers(&regs); in Run()
221 const auto registers = Span<VReg *>(regs.data(), regs.data() + regCnt); in Run()
/arkcompiler/runtime_core/static_core/assembler/
Dassembly-ins.cpp24 for (const auto &reg : this->regs) { in RegsToString()
88 if (idx >= regs.size()) { in RegToString()
100 if (printArgs && regs[idx] >= firstArgIdx) { in RegToString()
101 translator << "a" << regs[idx] - firstArgIdx; in RegToString()
103 translator << "v" << regs[idx]; in RegToString()
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
Dcallconv.cpp65 void Aarch64CallingConvention::PrepareToPushPopRegs(vixl::aarch64::CPURegList regs, vixl::aarch64::… in PrepareToPushPopRegs() argument
68 if ((regs.GetCount() % IMM_2) == 1) { in PrepareToPushPopRegs()
69 ASSERT((regs.GetList() & (UINT64_C(1) << vixl::aarch64::xzr.GetCode())) == 0); in PrepareToPushPopRegs()
70 regs.Combine(vixl::aarch64::xzr); in PrepareToPushPopRegs()
80 size_t Aarch64CallingConvention::PushRegs(vixl::aarch64::CPURegList regs, vixl::aarch64::CPURegList… in PushRegs() argument
83 PrepareToPushPopRegs(regs, vregs, isCallee); in PushRegs()
85 GetMasm()->PushCPURegList(regs); in PushRegs()
86 return vregs.GetCount() + regs.GetCount(); in PushRegs()
89 size_t Aarch64CallingConvention::PopRegs(vixl::aarch64::CPURegList regs, vixl::aarch64::CPURegList … in PopRegs() argument
91 PrepareToPushPopRegs(regs, vregs, isCallee); in PopRegs()
[all …]
/arkcompiler/runtime_core/static_core/disassembler/templates/
Dbc_ins_to_pandasm_ins.cpp.erb46 ins.regs.emplace_back(bcIns.GetVReg(<%=reg_count%>));
86 overhead = ins.regs.size() - pda.GetNumArgs();
88 overhead = ins.regs.size() - pda.GetNumArgs() - 1;
94 if (overhead < 0 || overhead > static_cast<int>(ins.regs.size())) {
105 ins.regs.pop_back();
/arkcompiler/runtime_core/assembler/
Dassembly-ins.cpp25 for (const auto &reg : this->Regs()) { in RegsToString()
90 if (idx >= Regs().size()) { in RegToString()
102 if (print_args && Regs()[idx] >= first_arg_idx) { in RegToString()
103 translator << "a" << Regs()[idx] - first_arg_idx; in RegToString()
105 translator << "v" << Regs()[idx]; in RegToString()
/arkcompiler/runtime_core/static_core/abc2program/templates/
Dabc_inst_convert.cpp.erb55 ins.regs.emplace_back(bcIns.GetVReg(<%=reg_count%>));
95 overhead = ins.regs.size() - pda.GetNumArgs();
97 overhead = ins.regs.size() - pda.GetNumArgs() - 1;
103 if (overhead < 0 || overhead > static_cast<int>(ins.regs.size())) {
114 ins.regs.pop_back();

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