| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | aspeed-wdt.txt | 4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
20 This is useful in situations where another watchdog engine on chip is
21 to perform the reset.
23 If 'aspeed,reset-type=' is not specified the default is to enable system
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| D | cadence-wdt.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,wdt-r1p2".
6 - clocks : This is pclk (APB clock).
7 - interrupts : This is wd_irq - watchdog timeout interrupt.
10 - reset-on-timeout : If this property exists, then a reset is done
12 - timeout-sec : Watchdog timeout value (in seconds).
16 compatible = "cdns,wdt-r1p2";
18 interrupt-parent = <&intc>;
21 reset-on-timeout;
22 timeout-sec = <10>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/ |
| D | aspeed-wdt.txt | 4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspeed,reset-type = "cpu|soc|system|none"
16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
20 This is useful in situations where another watchdog engine on chip is
21 to perform the reset.
23 If 'aspeed,reset-type=' is not specified the default is to enable system
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| D | cdns,wdt-r1p2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
15 a programmable reset period. The timeout period varies from 1 ms
19 - $ref: watchdog.yaml#
24 - cdns,wdt-r1p2
35 reset-on-timeout:
38 If this property exists, then a reset is done when watchdog
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| D | Kconfig.profile | 2 int "Default timeout for requests (ms)"
5 Configures the default timeout after which any user submissions will
13 May be 0 to disable the timeout.
16 int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
21 make forward progress. This value specifies the timeout used for an
24 May be 0 to disable the timeout, and rely on the foreign fence being
31 On runtime suspend, as we suspend the device, we have to revoke
32 userspace GGTT mmaps and force userspace to take a pagefault on
35 that complements the runtime-pm autosuspend and provides a lower
36 floor on the autosuspend delay.
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| /kernel/linux/linux-6.6/Documentation/watchdog/ |
| D | mlx-wdt.rst | 16 Actual HW timeout can be defined as a power of 2 msec.
17 e.g. timeout 20 sec will be rounded up to 32768 msec.
18 The maximum timeout period is 32 sec (32768 msec.),
19 Get time-left isn't supported
22 Actual HW timeout is defined in sec. and it's the same as
23 a user-defined timeout.
24 Maximum timeout is 255 sec.
25 Get time-left is supported.
28 Same as Type 2 with extended maximum timeout period.
29 Maximum timeout is 65535 sec.
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| D | watchdog-api.rst | 9 Copyright 2002 Christer Weingel <wingel@nano-system.com>
19 A Watchdog Timer (WDT) is a hardware circuit that can reset the
27 that the watchdog should wait for yet another little while to reset
29 notifications cease to occur, and the hardware watchdog will reset the
30 system (causing a reboot) after the timeout occurs.
32 The Linux watchdog API is a rather ad-hoc construction and different
43 timeout or margin. The simplest way to ping the watchdog is to write
45 like this source file: see samples/watchdog/watchdog-simple.c
54 drivers support the configuration option "Disable watchdog shutdown on
58 after the timeout has passed. Watchdog devices also usually support
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| /kernel/linux/linux-5.10/Documentation/watchdog/ |
| D | mlx-wdt.rst | 16 Actual HW timeout can be defined as a power of 2 msec.
17 e.g. timeout 20 sec will be rounded up to 32768 msec.
18 The maximum timeout period is 32 sec (32768 msec.),
19 Get time-left isn't supported
22 Actual HW timeout is defined in sec. and it's the same as
23 a user-defined timeout.
24 Maximum timeout is 255 sec.
25 Get time-left is supported.
28 Same as Type 2 with extended maximum timeout period.
29 Maximum timeout is 65535 sec.
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| D | watchdog-api.rst | 9 Copyright 2002 Christer Weingel <wingel@nano-system.com>
19 A Watchdog Timer (WDT) is a hardware circuit that can reset the
27 that the watchdog should wait for yet another little while to reset
29 notifications cease to occur, and the hardware watchdog will reset the
30 system (causing a reboot) after the timeout occurs.
32 The Linux watchdog API is a rather ad-hoc construction and different
43 timeout or margin. The simplest way to ping the watchdog is to write
45 like this source file: see samples/watchdog/watchdog-simple.c
54 drivers support the configuration option "Disable watchdog shutdown on
58 after the timeout has passed. Watchdog devices also usually support
[all …]
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | cadence_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
63 * struct cdns_wdt - Watchdog device structure
65 * @rst: reset flag
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
99 * Zero Mode Register - This register controls how the time out is indicated
103 #define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
105 #define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
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| D | sb_wdog.c | 7 * on the Sibyte 12XX and 11XX SoCs available to the user. There are two
8 * such devices available on the SoC, but it seems that there isn't an
13 * I have not tried this driver on a 1480 processor; it might work
18 * is reset and there is no way to redirect that NMI. Which could
19 * be problematic in some cases where this chip is sitting on the HT
21 * Since the reset can't be redirected to the external reset pin, it is
22 * possible that other HT connected processors might hang and not reset.
23 * For Linux, a soft reset would probably be even worse than a hard reset.
35 * Based on various other watchdog drivers, which are probably all
36 * loosely based on something Alan Cox wrote years ago.
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| D | pnx833x_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Heavily based upon - IndyDog 0.3
13 * based on softdog.c by Alan Cox <alan@redhat.com>
29 #include <asm/mach-pnx833x/pnx833x.h>
31 #define WATCHDOG_TIMEOUT 30 /* 30 sec Maximum timeout */
42 /** RESET block */
48 /* Set default timeout in MHZ.*/
51 MODULE_PARM_DESC(timeout, "Watchdog timeout in Mhz. (68Mhz clock), default="
62 MODULE_PARM_DESC(start_enabled, "Watchdog is started on module insertion "
67 /* Enable watchdog causing reset. */ in pnx833x_wdt_start()
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| D | imx2_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
14 * ---- -----
15 * Registers: 32-bit 16-bit
18 * Halt on suspend: Manual Can be automatic
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39 #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40 #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41 #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
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| D | smsc37b787_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on acquirewdt.c by Alan Cox <alan@lxorguk.ukuu.org.uk>
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
22 * reset the computer system in case of a software fault.
30 * for yet another little while to reset the system.
33 * reset the system (causing a reboot) after the timeout occurs.
38 * For an example userspace keep-alive daemon, see:
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | cadence_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
63 * struct cdns_wdt - Watchdog device structure
65 * @rst: reset flag
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
99 * Zero Mode Register - This register controls how the time out is indicated
103 #define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
105 #define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
[all …]
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| D | sb_wdog.c | 7 * on the Sibyte 12XX and 11XX SoCs available to the user. There are two
8 * such devices available on the SoC, but it seems that there isn't an
13 * I have not tried this driver on a 1480 processor; it might work
18 * is reset and there is no way to redirect that NMI. Which could
19 * be problematic in some cases where this chip is sitting on the HT
21 * Since the reset can't be redirected to the external reset pin, it is
22 * possible that other HT connected processors might hang and not reset.
23 * For Linux, a soft reset would probably be even worse than a hard reset.
35 * Based on various other watchdog drivers, which are probably all
36 * loosely based on something Alan Cox wrote years ago.
[all …]
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| D | smsc37b787_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on acquirewdt.c by Alan Cox <alan@lxorguk.ukuu.org.uk>
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
22 * reset the computer system in case of a software fault.
30 * for yet another little while to reset the system.
33 * reset the system (causing a reboot) after the timeout occurs.
38 * For an example userspace keep-alive daemon, see:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | nvidia,tegra20-sdhci.txt | 3 This controller on Tegra family SoCs provides an interface for MMC, SD,
7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
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| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | fsi.h | 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
26 #define SCOM_INTF_ERR_ABORT 0x00000004 /* PIB reset during access */
33 __u8 pib_status; /* 3-bit PIB status */
40 #define SCOM_PIB_PARITY_ERR 6 /* Parity error on the PIB bus */
41 #define SCOM_PIB_TIMEOUT 7 /* Bus timeout */
49 /* Flags for SCOM reset */
50 #define SCOM_RESET_INTF 0x00000001 /* Reset interface */
51 #define SCOM_RESET_PIB 0x00000002 /* Reset PIB */
63 * FSI_SBEFIFO_CMD_TIMEOUT sets the timeout for writing data to the SBEFIFO.
65 * The command timeout is specified in seconds. The minimum value of command
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| D | Kconfig.profile | 2 int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
7 make forward progress. This value specifies the timeout used for an
10 May be 0 to disable the timeout, and rely on the foreign fence being
17 On runtime suspend, as we suspend the device, we have to revoke
18 userspace GGTT mmaps and force userspace to take a pagefault on
21 that complements the runtime-pm autosuspend and provides a lower
22 floor on the autosuspend delay.
32 check the health of the GPU and undertake regular house-keeping of
42 int "Preempt timeout (ms, jiffy granularity)"
48 expires, the HW will be reset to allow the more important context
[all …]
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| /kernel/linux/linux-6.6/drivers/fsi/ |
| D | fsi-sbefifo.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/fsi-sbefifo.h>
38 * The SBEFIFO is a pipe-like FSI device for communicating with
39 * the self boot engine on POWER processors.
50 #define SBEFIFO_UP 0x00 /* FSI -> Host */
51 #define SBEFIFO_DOWN 0x40 /* Host -> FSI */
53 /* Per-bank registers */
69 #define SBEFIFO_REQ_RESET 0x0C /* (Up only) Reset Request */
70 #define SBEFIFO_PERFORM_RESET 0x10 /* (Down only) Perform Reset */
85 SBE_STATE_IPLING = 0x1, // IPL'ing - autonomous mode (transient)
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| /kernel/linux/linux-6.6/arch/arm/mach-meson/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/reset.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
113 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
119 * Set the entry point before powering on the CPU through the SCU. This in meson_smp_begin_secondary_boot()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
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| /kernel/linux/linux-5.10/arch/arm/mach-meson/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/reset.h>
23 #define MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(c) (0x04 + ((c - 1) << 2))
31 #define MESON_CPU_PWR_A9_MEM_PD0_M(c) (0x0f << (32 - (c * 4)))
106 meson_smp_prepare_cpus("arm,cortex-a5-scu", "amlogic,meson8b-pmu", in meson8b_smp_prepare_cpus()
107 "amlogic,meson8b-smp-sram"); in meson8b_smp_prepare_cpus()
112 meson_smp_prepare_cpus("arm,cortex-a9-scu", "amlogic,meson8-pmu", in meson8_smp_prepare_cpus()
113 "amlogic,meson8-smp-sram"); in meson8_smp_prepare_cpus()
119 * Set the entry point before powering on the CPU through the SCU. This in meson_smp_begin_secondary_boot()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
[all …]
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| /kernel/linux/linux-5.10/drivers/ide/ |
| D | ide-eh.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 ide_hwif_t *hwif = drive->hwif; in ide_ata_error()
14 ((stat & ATA_DF) && (drive->dev_flags & IDE_DFLAG_NOWERR) == 0)) { in ide_ata_error()
16 scsi_req(rq)->result |= ERROR_RESET; in ide_ata_error()
18 /* err has different meaning on cdrom and tape */ in ide_ata_error()
20 if ((drive->dev_flags & IDE_DFLAG_LBA) && in ide_ata_error()
22 hwif->tp_ops->read_status(hwif) == ATA_CMD_INIT_DEV_PARAMS) in ide_ata_error()
26 drive->crc_count++; in ide_ata_error()
29 scsi_req(rq)->result = ERROR_MAX; in ide_ata_error()
32 scsi_req(rq)->result |= ERROR_RECAL; in ide_ata_error()
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| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-ali1535.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 This is the driver for the SMB Host controller on
22 by comparing this driver to the i2c-ali15x3 driver.
26 ACPI-compliant Power Management Unit (PMU).
87 #define ALI1535_DEV10B_EN 0x80 /* Enable 10-bit addressing in */
89 #define ALI1535_T_OUT 0x08 /* Time-out Command (write) */
90 #define ALI1535_A_HIGH_BIT9 0x08 /* Bit 9 of 10-bit address in */
91 /* Alert-Response-Address */
94 #define ALI1535_A_HIGH_BIT8 0x04 /* Bit 8 of 10-bit address in */
95 /* Alert-Response-Address */
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