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/kernel/linux/linux-6.6/arch/arm/mach-mvebu/
Dmvebu-soc-id.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ID and revision information for mvebu SoCs
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * revision that can be read from the PCI control register. This is
12 * ID and revision are retrieved, the mapping is freed.
15 #define pr_fmt(fmt) "mvebu-soc-id: " fmt
26 #include "mvebu-soc-id.h"
39 { .compatible = "marvell,armada-xp-pcie", },
40 { .compatible = "marvell,armada-370-pcie", },
41 { .compatible = "marvell,kirkwood-pcie" },
[all …]
Dmvebu-soc-id.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Marvell EBU SoC ID and revision definitions.
11 /* Armada XP ID */
16 /* Armada XP Revision */
20 /* Amada 370 ID */
23 /* Amada 370 Revision */
26 /* Armada 375 ID */
33 /* Armada 38x ID */
38 /* Armada 38x Revision */
47 return -1; in mvebu_get_soc_id()
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
Dmvebu-soc-id.c2 * ID and revision information for mvebu SoCs
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 * revision that can be read from the PCI control register. This is
15 * ID and revision are retrieved, the mapping is freed.
18 #define pr_fmt(fmt) "mvebu-soc-id: " fmt
29 #include "mvebu-soc-id.h"
42 { .compatible = "marvell,armada-xp-pcie", },
43 { .compatible = "marvell,armada-370-pcie", },
44 { .compatible = "marvell,kirkwood-pcie" },
55 return -ENODEV; in mvebu_get_soc_id()
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Dmvebu-soc-id.h2 * Marvell EBU SoC ID and revision definitions.
14 /* Armada XP ID */
19 /* Armada XP Revision */
23 /* Amada 370 ID */
26 /* Amada 370 Revision */
29 /* Armada 375 ID */
36 /* Armada 38x ID */
41 /* Armada 38x Revision */
50 return -1; in mvebu_get_soc_id()
/kernel/linux/linux-6.6/drivers/ssb/
Ddriver_chipcommon.c7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
45 struct ssb_device *ccdev = cc->dev; in ssb_chipco_set_clockmode()
51 bus = ccdev->bus; in ssb_chipco_set_clockmode()
54 if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) in ssb_chipco_set_clockmode()
57 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) in ssb_chipco_set_clockmode()
59 WARN_ON(ccdev->id.revision >= 20); in ssb_chipco_set_clockmode()
62 if (ccdev->id.revision < 6) in ssb_chipco_set_clockmode()
66 if (ccdev->id.revision >= 10) in ssb_chipco_set_clockmode()
69 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in ssb_chipco_set_clockmode()
79 if (ccdev->id.revision < 10) { in ssb_chipco_set_clockmode()
[all …]
/kernel/linux/linux-5.10/drivers/ssb/
Ddriver_chipcommon.c7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
45 struct ssb_device *ccdev = cc->dev; in ssb_chipco_set_clockmode()
51 bus = ccdev->bus; in ssb_chipco_set_clockmode()
54 if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) in ssb_chipco_set_clockmode()
57 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) in ssb_chipco_set_clockmode()
59 WARN_ON(ccdev->id.revision >= 20); in ssb_chipco_set_clockmode()
62 if (ccdev->id.revision < 6) in ssb_chipco_set_clockmode()
66 if (ccdev->id.revision >= 10) in ssb_chipco_set_clockmode()
69 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) in ssb_chipco_set_clockmode()
79 if (ccdev->id.revision < 10) { in ssb_chipco_set_clockmode()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/
Ddiscovery.h79 uint32_t id; /* Table ID */ member
94 uint16_t hw_id; /* Hardware ID */
99 uint8_t revision; /* HCID Revision */ member
112 uint16_t hw_id; /* Hardware ID */
115 uint8_t major; /* Hardware ID.major version */
116 uint8_t minor; /* Hardware ID.minor version */
117 uint8_t revision; /* Hardware ID.revision version */ member
120 uint8_t sub_revision : 4; /* HCID Sub-Revision */
122 uint8_t sub_revision : 4; /* HCID Sub-Revision */
129 uint16_t hw_id; /* Hardware ID */
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/kernel/linux/linux-6.6/drivers/soc/samsung/
Dexynos-chipid.c1 // SPDX-License-Identifier: GPL-2.0
7 * Exynos - CHIP ID support
12 * Samsung Exynos SoC Adaptive Supply Voltage and Chip ID support
23 #include <linux/soc/samsung/exynos-chipid.h>
26 #include "exynos-asv.h"
29 unsigned int rev_reg; /* revision register offset */
30 unsigned int main_rev_shift; /* main revision offset in rev_reg */
31 unsigned int sub_rev_shift; /* sub revision offset in rev_reg */
36 u32 revision; member
41 unsigned int id; member
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/kernel/linux/linux-5.10/drivers/soc/samsung/
Dexynos-chipid.c1 // SPDX-License-Identifier: GPL-2.0
6 * Exynos - CHIP ID support
16 #include <linux/soc/samsung/exynos-chipid.h>
21 unsigned int id; member
24 { "EXYNOS4210", 0x43200000 }, /* EVT0 revision */
43 if ((product_id & EXYNOS_MASK) == soc_ids[i].id) in product_id_to_soc_id()
56 u32 revision; in exynos_chipid_early_init() local
60 "samsung,exynos4210-chipid"); in exynos_chipid_early_init()
62 return -ENODEV; in exynos_chipid_early_init()
74 revision = product_id & EXYNOS_REV_MASK; in exynos_chipid_early_init()
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/kernel/linux/linux-6.6/drivers/scsi/mvsas/
Dmv_94xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_detect_porttype()
23 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); in mvs_94xx_detect_porttype()
26 phy->phy_type |= PORT_TYPE_SAS; in mvs_94xx_detect_porttype()
30 phy->phy_type |= PORT_TYPE_SATA; in mvs_94xx_detect_porttype()
43 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) in set_phy_tuning()
44 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) in set_phy_tuning()
45 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) in set_phy_tuning()
46 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) in set_phy_tuning()
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/kernel/linux/linux-5.10/drivers/scsi/mvsas/
Dmv_94xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
17 struct mvs_phy *phy = &mvi->phy[i]; in mvs_94xx_detect_porttype()
23 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); in mvs_94xx_detect_porttype()
26 phy->phy_type |= PORT_TYPE_SAS; in mvs_94xx_detect_porttype()
30 phy->phy_type |= PORT_TYPE_SATA; in mvs_94xx_detect_porttype()
43 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient) in set_phy_tuning()
44 * R0Dh -> R118h[31:16] (Generation 1 Setting 0) in set_phy_tuning()
45 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1) in set_phy_tuning()
46 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0) in set_phy_tuning()
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/kernel/linux/linux-5.10/drivers/watchdog/
Dpcwd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 960108 Fixed end-of-file pointer (Thanks to Dan Hollis), added
24 * added watchdog disable/re-enable routines. Added firmware
26 * Removed some extra defines, added an autodetect Revision
60 #include <linux/errno.h> /* For the -ENODEV/... values */
71 #include <linux/ioport.h> /* For io-port access */
79 #define WATCHDOG_DRIVER_NAME "ISA-PC Watchdog"
94 * These are the auto-probe addresses available.
96 * Revision A only uses ports 0x270 and 0x370. Revision C introduced 0x350.
97 * Revision A has an address range of 2 addresses, while Revision C has 4.
[all …]
/kernel/linux/linux-6.6/drivers/watchdog/
Dpcwd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * 960108 Fixed end-of-file pointer (Thanks to Dan Hollis), added
24 * added watchdog disable/re-enable routines. Added firmware
26 * Removed some extra defines, added an autodetect Revision
60 #include <linux/errno.h> /* For the -ENODEV/... values */
71 #include <linux/ioport.h> /* For io-port access */
79 #define WATCHDOG_DRIVER_NAME "ISA-PC Watchdog"
94 * These are the auto-probe addresses available.
96 * Revision A only uses ports 0x270 and 0x370. Revision C introduced 0x350.
97 * Revision A has an address range of 2 addresses, while Revision C has 4.
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/kernel/linux/linux-6.6/kernel/bpf/
Dmprog.c1 // SPDX-License-Identifier: GPL-2.0
11 struct bpf_link *link = ERR_PTR(-EINVAL); in bpf_mprog_link()
12 bool id = flags & BPF_F_ID; in bpf_mprog_link() local
14 if (id) in bpf_mprog_link()
20 if (type && link->prog->type != type) { in bpf_mprog_link()
22 return -EINVAL; in bpf_mprog_link()
25 tuple->link = link; in bpf_mprog_link()
26 tuple->prog = link->prog; in bpf_mprog_link()
34 struct bpf_prog *prog = ERR_PTR(-EINVAL); in bpf_mprog_prog()
35 bool id = flags & BPF_F_ID; in bpf_mprog_prog() local
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/kernel/linux/linux-5.10/drivers/soc/imx/
Dsoc-imx8m.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/arm-smccc.h>
60 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp"); in imx8mq_soc_revision()
68 * SOC revision on older imx8mq is not available in fuses so query in imx8mq_soc_revision()
95 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp"); in imx8mm_soc_uid()
116 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); in imx8mm_soc_revision()
170 const struct of_device_id *id; in imx8_soc_init() local
177 return -ENOMEM; in imx8_soc_init()
179 soc_dev_attr->family = "Freescale i.MX"; in imx8_soc_init()
181 ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine); in imx8_soc_init()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_cgs.c41 ((struct amdgpu_cgs_device *)cgs_device)->adev
142 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert()
167 fw_version = adev->sdma.instance[0].fw_version; in amdgpu_get_firmware_version()
170 fw_version = adev->sdma.instance[1].fw_version; in amdgpu_get_firmware_version()
173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
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/kernel/linux/linux-5.10/fs/cifs/
Dcifsacl.c21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/key-type.h>
29 #include <keys/user-type.h>
36 /* security id for everyone/world system group */
39 /* security id for Authenticated Users system group */
43 /* S-1-22-1 Unmapped Unix users */
47 /* S-1-22-2 Unmapped Unix groups */
52 * See https://technet.microsoft.com/en-us/library/hh509017(v=ws.10).aspx
55 /* S-1-5-88 MS NFS and Apple style UID/GID/mode */
57 /* S-1-5-88-1 Unix uid */
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
10 int revision; member
66 { .id = 0, .pp = 0, .dspp = 0,
68 { .id = 1, .pp = 1, .dspp = 1,
70 { .id = 2, .pp = 2, .dspp = 2,
72 { .id = 3, .pp = -1, .dspp = -1,
74 { .id = 4, .pp = -1, .dspp = -1,
144 { .id = 0, .pp = 0, .dspp = 0,
146 { .id = 1, .pp = 1, .dspp = 1,
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser2.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 bp->base.ctx->logger
88 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
92 kfree(bp->base.bios_local_image); in bios_parser2_destruct()
93 kfree(bp->base.integrated_info); in bios_parser2_destruct()
118 /* initialize the revision to 0 which is invalid revision */ in get_atom_data_table_revision()
119 tbl_revision->major = 0; in get_atom_data_table_revision()
120 tbl_revision->minor = 0; in get_atom_data_table_revision()
125 tbl_revision->major = in get_atom_data_table_revision()
126 (uint32_t) atom_data_tbl->format_revision & 0x3f; in get_atom_data_table_revision()
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/kernel/linux/linux-6.6/drivers/soc/aspeed/
Daspeed-socinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 const u32 id; member
34 unsigned int id = siliconid & 0xff00ffff; in siliconid_to_name() local
38 if (rev_table[i].id == id) in siliconid_to_name()
88 np = of_find_compatible_node(NULL, NULL, "aspeed,silicon-id"); in aspeed_socinfo_init()
91 return -ENODEV; in aspeed_socinfo_init()
97 return -ENODEV; in aspeed_socinfo_init()
114 return -ENODEV; in aspeed_socinfo_init()
119 * Revision: A1 in aspeed_socinfo_init()
120 * SoC ID: raw silicon revision id in aspeed_socinfo_init()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
10 int revision; member
66 { .id = 0, .pp = 0, .dspp = 0,
68 { .id = 1, .pp = 1, .dspp = 1,
70 { .id = 2, .pp = 2, .dspp = 2,
72 { .id = 3, .pp = -1, .dspp = -1,
74 { .id = 4, .pp = -1, .dspp = -1,
155 { .id = 0, .pp = 0, .dspp = 0,
157 { .id = 1, .pp = -1, .dspp = -1,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/panfrost/
Dpanfrost_gpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", in panfrost_gpu_irq_handler()
40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); in panfrost_gpu_irq_handler()
65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, in panfrost_gpu_soft_reset()
69 dev_err(pfdev->dev, "gpu soft reset timed out\n"); in panfrost_gpu_soft_reset()
82 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs in panfrost_gpu_amlogic_quirk()
129 /* Limit read & write ID width for AXI */ in panfrost_gpu_init_quirks()
141 pfdev->features.revision >= 0x2000) in panfrost_gpu_init_quirks()
144 pfdev->features.coherency_features == COHERENCY_ACE) in panfrost_gpu_init_quirks()
[all …]
/kernel/linux/linux-5.10/arch/mips/pci/
Dfixup-cobalt.c33 * The Cobalt board ID information. The boards have an ID number wired
41 if (dev->devfn == PCI_DEVFN(0, 0) && in qube_raq_galileo_early_fixup()
42 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { in qube_raq_galileo_early_fixup()
44 dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); in qube_raq_galileo_early_fixup()
78 if (dev->devfn != PCI_DEVFN(0, 0)) in qube_raq_galileo_fixup()
81 /* Fix PCI latency-timer and cache-line-size values in Galileo in qube_raq_galileo_fixup()
93 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- in qube_raq_galileo_fixup()
103 printk(KERN_INFO "Galileo: revision %u\n", dev->revision); in qube_raq_galileo_fixup()
106 if (dev->revision >= 0x10) { in qube_raq_galileo_fixup()
109 } else if (dev->revision == 0x1 || dev->revision == 0x2) in qube_raq_galileo_fixup()
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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/kernel/linux/linux-6.6/include/linux/
Dmcb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 * struct mcb_bus - MEN Chameleon Bus
27 * @revision: the FPGA's revision number
35 u8 revision; member
48 * struct mcb_device - MEN Chameleon Bus device
54 * @id: mcb device id
59 * @rev: revision in Chameleon table
67 u16 id; member
81 * struct mcb_driver - MEN Chameleon Bus device driver
84 * @id_table: mcb id table
[all …]

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