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/kernel/linux/linux-5.10/include/sound/
Dcs8427.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
68 #define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
88 #define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */
89 #define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */
[all …]
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
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Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
[all …]
/kernel/linux/linux-6.6/include/sound/
Dcs8427.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */
34 #define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */
63 #define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
65 #define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */
66 #define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */
68 #define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */
69 #define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */
88 #define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */
89 #define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */
[all …]
Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
[all …]
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
[all …]
Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
[all …]
/kernel/linux/linux-6.6/Documentation/sound/soc/
Ddai.rst28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
35 I2S has several different operating modes:-
41 Left Justified
44 Right Justified
58 Common PCM operating modes:-
/kernel/linux/linux-5.10/Documentation/sound/soc/
Ddai.rst28 left/right clock (LRC) synchronise the link. I2S is flexible in that either the
35 I2S has several different operating modes:-
41 Left Justified
44 Right Justified
58 Common PCM operating modes:-
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Justified Mode, Right Justified Mode, and DSP mode formats.
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
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Dst,stm32-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@foss.st.com>
14 protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
15 The SAI contains two independent audio sub-blocks. Each sub-block has
21 - st,stm32f4-sai
22 - st,stm32h7-sai
26 - description: Base address and size of SAI common register set.
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Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
[all …]
Dcirrus,ep9301-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/cirrus,ep9301-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 I2S CODECs’, ADCs/DACs, and the ARM Core. The controller supports I2S, Left-
12 and Right-Justified DSP formats.
15 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
18 - $ref: dai-common.yaml#
22 const: cirrus,ep9301-i2s
24 '#sound-dai-cells':
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/kernel/linux/linux-5.10/drivers/s390/crypto/
Dzcrypt_cex2a.h1 /* SPDX-License-Identifier: GPL-2.0+ */
19 * Note that all unsigned char arrays are right-justified and left-padded
42 /* Mod-Exp, with a small modulus */
52 /* Mod-Exp, with a large modulus */
62 /* Mod-Exp, with a larger modulus */
114 * Note that all unsigned char arrays are right-justified and left-padded
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dst,stm32-sai.txt4 as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
5 The SAI contains two independent audio sub-blocks. Each sub-block has
9 - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai"
10 - reg: Base address and size of SAI common register set.
11 - clocks: Must contain phandle and clock specifier pairs for each entry
12 in clock-names.
13 - clock-names: Must contain "pclk" "x8k" and "x11k"
15 Mandatory for "st,stm32h7-sai" compatible.
16 Not used for "st,stm32f4-sai" compatible.
19 - interrupts: cpu DAI interrupt line shared by SAI sub-blocks
[all …]
Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
[all …]
/kernel/linux/linux-5.10/include/sound/sof/
Ddai.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
13 #include <sound/sof/dai-intel.h>
14 #include <sound/sof/dai-imx.h>
23 #define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
24 #define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */
61 uint32_t type; /**< DAI type - enum sof_ipc_dai_type */
/kernel/linux/linux-6.6/sound/soc/codecs/
Dtlv320aic26.h1 /* SPDX-License-Identifier: GPL-2.0 */
79 AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */
80 AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */
Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
33 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
46 if (rk817->mic_in_differential) { in rk817_init()
62 /* Set the PLL pre-divide value (values not documented). */ in rk817_set_component_pll()
74 * 0db~-95db, 0.375db/step, for example:
76 * 0xff: -95dB
79 static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
83 * 27db~-18db, 3db/step, for example:
84 * 0x0: -18dB
88 static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dtlv320aic26.h1 /* SPDX-License-Identifier: GPL-2.0 */
79 AIC26_DATFM_RIGHTJ = 2 << 8, /* right justified */
80 AIC26_DATFM_LEFTJ = 3 << 8, /* left justified */
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
DTODO.txt2 -----------------
4 - For discrete memory manager, merge enough dg1 to be able to refactor it to
8 - Come up with a plan what to do with drm/scheduler and how to get there.
10 - Roll out dma_fence critical section annotations.
12 - There's a lot of complexity added past few years to make relocations faster.
15 1. Land a modern pre-bound uapi like VM_BIND
16 2. Any complexity added in this area past few years which can't be justified
23 - i915_sw_fence seems to be the main structure for the i915-gem dma_fence model.
24 How-to-dma_fence is core and drivers really shouldn't build their own world
27 removed if dri-devel consensus is that it's not a good idea. Once that's done
[all …]
/kernel/linux/linux-6.6/include/sound/sof/
Ddai.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
13 #include <sound/sof/dai-intel.h>
14 #include <sound/sof/dai-imx.h>
15 #include <sound/sof/dai-amd.h>
16 #include <sound/sof/dai-mediatek.h>
25 #define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
26 #define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */
96 uint32_t type; /**< DAI type - enum sof_ipc_dai_type */
/kernel/linux/linux-6.6/arch/parisc/math-emu/
Dfpbits.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
10 PA header file -- do not include this header file for non-PA builds.
18 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11)
20 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20).
22 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the
33 /*-------------------------------------------------------------------------
34 * NewDeclareBitField_Reference - Declare a structure similar to the simulator
[all …]
/kernel/linux/linux-5.10/arch/parisc/math-emu/
Dfpbits.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
5 * Floating-point emulation code
6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org>
10 PA header file -- do not include this header file for non-PA builds.
18 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11)
20 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20).
22 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the
33 /*-------------------------------------------------------------------------
34 * NewDeclareBitField_Reference - Declare a structure similar to the simulator
[all …]

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