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/kernel/linux/linux-6.6/arch/riscv/
DMakefile2 # architecture-specific flags and dependencies.
9 LDFLAGS_vmlinux := -z norelro
11 LDFLAGS_vmlinux += -shared -Bsymbolic -z notext --emit-relocs
12 KBUILD_CFLAGS += -fPIE
15 LDFLAGS_vmlinux += --no-relax
16 KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
18 CC_FLAGS_FTRACE := -fpatchable-function-entry=4
20 CC_FLAGS_FTRACE := -fpatchable-function-entry=2
25 KBUILD_CFLAGS_MODULE += -mcmodel=medany
33 KBUILD_CFLAGS += -mabi=lp64
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
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/kernel/linux/linux-5.10/arch/riscv/
DMakefile2 # architecture-specific flags and dependencies. Remember to do have actions
11 OBJCOPYFLAGS := -O binary
14 LDFLAGS_vmlinux := --no-relax
18 KBUILD_CFLAGS_MODULE += -mcmodel=medany
26 KBUILD_CFLAGS += -mabi=lp64
27 KBUILD_AFLAGS += -mabi=lp64
29 KBUILD_LDFLAGS += -melf64lriscv
34 KBUILD_CFLAGS += -mabi=ilp32
35 KBUILD_AFLAGS += -mabi=ilp32
36 KBUILD_LDFLAGS += -melf32lriscv
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
99 # VA_BITS - PAGE_SHIFT - 3
109 # set if we are running in S-mode and can use SBI calls
116 bool "MMU-based Paged Memory Management Support"
119 Select if you want MMU-based virtualised addressing space
205 source "arch/riscv/Kconfig.socs"
275 bool "Symmetric Multi-Processing"
288 int "Maximum number of CPUs (2-32)"
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/kernel/linux/linux-6.6/Documentation/riscv/
Dvector.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
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/kernel/linux/linux-5.10/Documentation/riscv/
Dpmu.rst2 Supporting PMUs on RISC-V platforms
8 ------------
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
23 Counters are just free-running all the time in our case.
25 No such feature in the spec.
33 hardware-extension for M-S-U model machines to write counters directly.
44 -----------------
47 various methods according to perf's internal convention and PMU-specific
53 the minimal and already-implemented logic can be leveraged, or invent his/her
63 -----------------------
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/kernel/linux/linux-6.6/arch/riscv/kernel/
Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
88 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
97 pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); in riscv_isa_extension_check()
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Dacpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V Specific Low-Level ACPI Boot Support
5 * Copyright (C) 2013-2014, Linaro Ltd.
12 * Copyright (C) 2021-2023, Ventana Micro Systems Inc.
13 * Author: Sunil V L <sunilvl@ventanamicro.com>
37 return -EINVAL; in parse_acpi()
47 return -EINVAL; /* Core will print when we return error */ in parse_acpi()
54 * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity
67 * FADT is required on riscv; retrieve it to check its presence in acpi_fadt_sanity_check()
75 return -ENODEV; in acpi_fadt_sanity_check()
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/kernel/linux/linux-5.10/arch/riscv/kernel/
Dperf_event.c1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
7 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
13 * Perf_events support for RISC-V platforms.
15 * Since the spec. (as of now, Priv-Spec 1.10) does not provide enough
19 * For platform portings, please check Documentations/riscv/pmu.txt.
144 if (config >= riscv_pmu->max_events) in riscv_map_hw_event()
145 return -EINVAL; in riscv_map_hw_event()
147 return riscv_pmu->hw_events[config]; in riscv_map_hw_event()
153 return -ENOENT; in riscv_map_cache_decode()
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/kernel/linux/linux-5.10/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
23 * This driver implements a version of the RISC-V PLIC with the actual layout
26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
30 * Spec.
87 u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); in plic_toggle()
90 raw_spin_lock(&handler->enable_lock); in plic_toggle()
95 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
104 writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
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/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-sifive-plic.c1 // SPDX-License-Identifier: GPL-2.0
24 * This driver implements a version of the RISC-V PLIC with the actual layout
27 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
30 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
31 * Spec.
106 raw_spin_lock(&handler->enable_lock); in plic_toggle()
107 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle()
108 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
119 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle()
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/kernel/linux/linux-6.6/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/kernel/linux/linux-6.6/Documentation/admin-guide/
Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
26 If set to vendor, prefer vendor-specific driver
58 Documentation/firmware-guide/acpi/debug.rst for more information about
116 Format: <byte> or <bitmap-list>
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/kernel/linux/linux-6.6/tools/lib/bpf/
Dlibbpf.c1 // SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
6 * Copyright (C) 2013-2015 Alexei Starovoitov <ast@kernel.org>
67 #pragma GCC diagnostic ignored "-Wformat-nonliteral"
260 if (err != -EPERM || geteuid() != 0) in pr_perm_msg()
277 pr_warn("permission error while running as root; try raising 'ulimit -l'? current value: %s\n", in pr_perm_msg()
293 fd = -1; \
304 /* as of v1.0 libbpf_set_strict_mode() is a no-op */ in libbpf_set_strict_mode()
322 return "v" _S(LIBBPF_MAJOR_VERSION) "." _S(LIBBPF_MINOR_VERSION); in libbpf_version_string()
350 /* stored as sec_def->cookie for all libbpf-supported SEC()s */
369 /* BPF program support non-linear XDP buffer */
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/kernel/linux/patches/linux-5.10/unionpi_tiger_pacth/
Dlinux-5.10.patch1 diff -Naur a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
2 --- a/arch/arm/boot/Makefile 2022-05-27 17:20:13.781877650 +0800
3 +++ b/arch/arm/boot/Makefile 2022-05-31 11:56:47.693259679 +0800
4 @@ -16,6 +16,7 @@
12 @@ -24,10 +25,12 @@
13 ZRELADDR := $(zreladdr-y)
14 PARAMS_PHYS := $(params_phys-y)
15 INITRD_PHYS := $(initrd_phys-y)
16 +DTB_OBJS ?= $(dtb-y)
21 -targets := Image zImage xipImage bootpImage uImage
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