Home
last modified time | relevance | path

Searched +full:rk2928 +full:- +full:pwm (Results 1 – 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-rockchip.txt1 Rockchip PWM controller
4 - compatible: should be "rockchip,<name>-pwm"
5 "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs
6 "rockchip,rk3288-pwm": found on RK3288 SOC
7 "rockchip,rv1108-pwm", "rockchip,rk3288-pwm": found on RV1108 SoC
8 "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
9 - reg: physical base address and length of the controller's registers
10 - clocks: See ../clock/clock-bindings.txt
11 - For older hardware (rk2928, rk3066, rk3188, rk3228, rk3288, rk3399):
12 - There is one clock that's used both to derive the functional clock
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dpwm-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PWM controller
10 - Heiko Stuebner <heiko@sntech.de>
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/rockchip/
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
18 arm-pmu {
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
16 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
15 #include <linux/pwm.h>
61 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
79 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
81 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
82 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
15 #include <linux/pwm.h>
61 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
77 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
78 tmp *= pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
[all …]
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch1 diff --git a/drivers/Makefile b/drivers/Makefile
3 --- a/drivers/Makefile
5 @@ -6,6 +6,8 @@
6 # Rewritten to use lists instead of if-statements.
11 obj-y += irqchip/
12 obj-y += bus/
14 diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
16 --- a/drivers/block/nbd.c
18 @@ -2398,12 +2398,6 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info)
22 - if (!dev_list) {
[all …]