| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | omap4-var-som-om44.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com
7 #include "omap4-mcpdm.dtsi"
10 model = "Variscite VAR-SOM-OM44";
11 compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
19 compatible = "ti,abe-twl6040";
20 ti,model = "VAR-SOM-OM44";
22 ti,mclk-freq = <38400000>;
27 ti,audio-routing =
36 compatible = "usb-nop-xceiv";
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx6ul-tqma6ul2l.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
12 model = "TQ-Systems TQMa6UL2L SoM";
13 compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
22 fsl,pins = <
33 /* rst */
[all …]
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| D | imx6ul-tqma6ul2.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6UL2 SoM";
13 compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
22 fsl,pins = <
33 /* rst */
[all …]
|
| D | imx6ull-tqma6ull2.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6ULL2 SoM";
13 compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
[all …]
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| D | imx6ull-tqma6ull2l.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
13 compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
21 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt6795-sony-xperia-m5.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "sony,xperia-m5", "mediatek,mt6795";
15 chassis-type = "handset";
30 reserved_memory: reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
38 no-map;
42 preloader-region@44800000 {
[all …]
|
| D | mt7986a-rfb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
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| D | mt8365-evk.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8mm-kontron-bl.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
8 #include "imx8mm-kontron-sl.dtsi"
12 compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
21 osc_can: clock-osc-can {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <16000000>;
25 clock-output-names = "osc-can";
29 compatible = "gpio-leds";
[all …]
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| D | imx8mm-kontron-bl-osm-s.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
8 #include "imx8mm-kontron-osm-s.dtsi"
11 model = "Kontron BL i.MX8MM OSM-S (N802X S)";
12 compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
19 osc_can: clock-osc-can {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <40000000>;
23 clock-output-names = "osc-can";
[all …]
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| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | ucd9000.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd90120.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd90124.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd90160.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd90320.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9090.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd90910.pdf
22 Author: Guenter Roeck <linux@roeck-us.net>
26 -----------
31 sequences up to 12 independent voltage rails. The device integrates a 12-bit
[all …]
|
| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | ucd9000.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd90120.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd90124.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd90160.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd90320.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9090.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd90910.pdf
22 Author: Guenter Roeck <linux@roeck-us.net>
26 -----------
31 sequences up to 12 independent voltage rails. The device integrates a 12-bit
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt7621-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
[all …]
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| D | mediatek,mt7620-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
[all …]
|
| /kernel/linux/linux-5.10/sound/soc/stm/ |
| D | stm32_sai.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
40 { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
41 { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
49 clk_disable_unprepare(sai->pclk); in stm32_sai_pclk_disable()
59 ret = clk_prepare_enable(sai->pclk); in stm32_sai_pclk_enable()
61 dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret); in stm32_sai_pclk_enable()
73 ret = stm32_sai_pclk_enable(&sai->pdev->dev); in stm32_sai_sync_conf_client()
77 writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base); in stm32_sai_sync_conf_client()
79 stm32_sai_pclk_disable(&sai->pdev->dev); in stm32_sai_sync_conf_client()
[all …]
|
| /kernel/linux/linux-6.6/sound/soc/stm/ |
| D | stm32_sai.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
40 { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
41 { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
49 clk_disable_unprepare(sai->pclk); in stm32_sai_pclk_disable()
59 ret = clk_prepare_enable(sai->pclk); in stm32_sai_pclk_enable()
61 dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret); in stm32_sai_pclk_enable()
73 ret = stm32_sai_pclk_enable(&sai->pdev->dev); in stm32_sai_sync_conf_client()
77 writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base); in stm32_sai_sync_conf_client()
79 stm32_sai_pclk_disable(&sai->pdev->dev); in stm32_sai_sync_conf_client()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | renesas,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/ |
| D | renesas,rst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/ |
| D | hikey970-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
|
| D | hikey960-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-falcon.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-falcon.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
22 #include "pinctrl-lantiq.h"
47 #define PINS 32 macro
48 #define PORT(x) (x / PINS)
49 #define PORT_PIN(x) (x % PINS)
67 .pins = p, \
90 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
95 int base = bank * PINS; in lantiq_load_pin_desc()
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-falcon.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-falcon.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
22 #include "pinctrl-lantiq.h"
47 #define PINS 32 macro
48 #define PORT(x) (x / PINS)
49 #define PORT_PIN(x) (x % PINS)
67 .pins = p, \
90 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
95 int base = bank * PINS; in lantiq_load_pin_desc()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | ste-hrefv60plus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href-ab8500.dtsi"
7 #include "ste-href.dtsi"
10 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
11 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
16 /* GPIOs 0 - 31 */
17 gpio-line-names =
38 /* GPIOs 32 - 63 */
39 gpio-line-names =
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | msm8916-pins.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default {
10 pins = "gpio0", "gpio1", "gpio2", "gpio3";
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep {
18 pins = "gpio0", "gpio1", "gpio2", "gpio3";
21 drive-strength = <2>;
22 bias-pull-down;
[all …]
|