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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reset/
Dhisilicon,hi3660-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
15 The reset controller registers are part of the system-ctl block on
21 - items:
22 - const: hisilicon,hi3660-reset
23 - items:
24 - const: hisilicon,hi3670-reset
[all …]
Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/microchip,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
25 - microchip,lan966x-switch-reset
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dcanaan,k210-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Damien Le Moal <dlemoal@kernel.org>
20 - const: canaan,k210-sysctl
21 - const: syscon
22 - const: simple-mfd
29 clock-names:
31 - const: pclk
[all …]
/kernel/linux/linux-6.6/drivers/reset/hisilicon/
Dreset-hi3660.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 #include <linux/mfd/syscon.h>
12 #include <linux/reset-controller.h>
15 struct reset_controller_dev rst; member
20 container_of(_rst, struct hi3660_reset_controller, rst)
30 return regmap_write(rc->map, offset, mask); in hi3660_reset_program_hw()
32 return regmap_write(rc->map, offset + 4, mask); in hi3660_reset_program_hw()
70 offset = reset_spec->args[0]; in hi3660_reset_xlate()
[all …]
/kernel/linux/linux-5.10/drivers/reset/hisilicon/
Dreset-hi3660.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
7 #include <linux/mfd/syscon.h>
12 #include <linux/reset-controller.h>
15 struct reset_controller_dev rst; member
20 container_of(_rst, struct hi3660_reset_controller, rst)
30 return regmap_write(rc->map, offset, mask); in hi3660_reset_program_hw()
32 return regmap_write(rc->map, offset + 4, mask); in hi3660_reset_program_hw()
70 offset = reset_spec->args[0]; in hi3660_reset_xlate()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dhisilicon,hi3660-reset.txt7 The reset controller registers are part of the system-ctl block on
11 - compatible: should be one of the following:
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
19 register from the syscon register base
26 compatible = "hisilicon,hi3660-iomcu", "syscon";
31 compatible = "hisilicon,hi3660-reset";
32 hisi,rst-syscon = <&iomcu>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
21 - compatible
26 - enum:
27 - starfive,jh7110-dwmac
[all …]
Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
/kernel/linux/linux-6.6/drivers/iio/adc/
Daspeed_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/clk-provider.h>
29 #include <linux/mfd/syscon.h>
117 struct reset_control *rst; member
178 struct device_node *syscon; in aspeed_adc_set_trim_data() local
183 syscon = of_find_node_by_name(NULL, "syscon"); in aspeed_adc_set_trim_data()
184 if (syscon == NULL) { in aspeed_adc_set_trim_data()
185 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data()
186 return -EOPNOTSUPP; in aspeed_adc_set_trim_data()
188 scu = syscon_node_to_regmap(syscon); in aspeed_adc_set_trim_data()
[all …]
/kernel/linux/linux-6.6/drivers/remoteproc/
Dstm32_rproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/arm-smccc.h>
9 #include <linux/dma-mapping.h>
13 #include <linux/mfd/syscon.h>
81 struct reset_control *rst; member
99 struct stm32_rproc *ddata = rproc->priv; in stm32_rproc_pa_to_da()
102 for (i = 0; i < ddata->nb_rmems; i++) { in stm32_rproc_pa_to_da()
103 p_mem = &ddata->rmems[i]; in stm32_rproc_pa_to_da()
105 if (pa < p_mem->bus_addr || in stm32_rproc_pa_to_da()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dbosch,c_can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dariobin@libero.it>
15 - $ref: can-controller.yaml#
20 - enum:
21 - bosch,c_can
22 - bosch,d_can
23 - ti,dra7-d_can
24 - ti,am3352-d_can
[all …]
/kernel/linux/linux-5.10/drivers/phy/socionext/
Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
12 #include <linux/mfd/syscon.h>
55 struct reset_control *rst, *rst_gio; member
68 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
69 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
70 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK; in uniphier_pciephy_set_param()
97 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_set_param()
104 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
/kernel/linux/linux-6.6/drivers/phy/socionext/
Dphy-uniphier-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller
12 #include <linux/mfd/syscon.h>
63 struct reset_control *rst, *rst_gio; member
80 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
81 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
87 u32 val = readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_read()
126 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
129 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
[all …]
/kernel/linux/linux-6.6/drivers/clk/visconti/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/mfd/syscon.h>
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
27 u32 rst = BIT(data->rs_idx); in visconti_reset_assert() local
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
42 u32 rst = BIT(data->rs_idx); in visconti_reset_deassert() local
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
[all …]
/kernel/linux/linux-5.10/drivers/remoteproc/
Dstm32_rproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/arm-smccc.h>
9 #include <linux/dma-mapping.h>
13 #include <linux/mfd/syscon.h>
80 struct reset_control *rst; member
97 struct stm32_rproc *ddata = rproc->priv; in stm32_rproc_pa_to_da()
100 for (i = 0; i < ddata->nb_rmems; i++) { in stm32_rproc_pa_to_da()
101 p_mem = &ddata->rmems[i]; in stm32_rproc_pa_to_da()
103 if (pa < p_mem->bus_addr || in stm32_rproc_pa_to_da()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
[all …]

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