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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/kernel/linux/linux-6.6/arch/s390/kernel/
Duprobes.c1 // SPDX-License-Identifier: GPL-2.0
3 * User-space Probes (UProbes) for s390
26 return probe_is_prohibited_opcode(auprobe->insn); in arch_uprobe_analyze_insn()
31 if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) in arch_uprobe_pre_xol()
32 return -EINVAL; in arch_uprobe_pre_xol()
33 if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) in arch_uprobe_pre_xol()
34 return -EINVAL; in arch_uprobe_pre_xol()
36 auprobe->saved_per = psw_bits(regs->psw).per; in arch_uprobe_pre_xol()
37 auprobe->saved_int_code = regs->int_code; in arch_uprobe_pre_xol()
38 regs->int_code = UPROBE_TRAP_NR; in arch_uprobe_pre_xol()
[all …]
/kernel/linux/linux-5.10/arch/s390/kernel/
Duprobes.c1 // SPDX-License-Identifier: GPL-2.0
3 * User-space Probes (UProbes) for s390
26 return probe_is_prohibited_opcode(auprobe->insn); in arch_uprobe_analyze_insn()
31 if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) in arch_uprobe_pre_xol()
32 return -EINVAL; in arch_uprobe_pre_xol()
33 if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) in arch_uprobe_pre_xol()
34 return -EINVAL; in arch_uprobe_pre_xol()
36 auprobe->saved_per = psw_bits(regs->psw).per; in arch_uprobe_pre_xol()
37 auprobe->saved_int_code = regs->int_code; in arch_uprobe_pre_xol()
38 regs->int_code = UPROBE_TRAP_NR; in arch_uprobe_pre_xol()
[all …]
/kernel/linux/linux-5.10/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
106 pabort("malformed input string"); in unescape()
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
124 .rx_buf = (unsigned long)rx, in transfer()
162 ret = write(out_fd, rx, len); in transfer()
170 hex_dump(rx, len, 32, "RX"); in transfer()
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/
Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
45 /* firmware RX pointer for new style buffer */
48 /* high parts of samples for fan input (8 samples)*/
52 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
66 /* fan as input settings */
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
[all …]
/kernel/linux/linux-6.6/drivers/media/rc/
Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
45 /* firmware RX pointer for new style buffer */
48 /* high parts of samples for fan input (8 samples)*/
52 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
66 /* fan as input settings */
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
[all …]
/kernel/linux/linux-6.6/tools/spi/
Dspidev_test.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
106 pabort("malformed input string"); in unescape()
118 static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len) in transfer() argument
124 .rx_buf = (unsigned long)rx, in transfer()
162 ret = write(out_fd, rx, len); in transfer()
170 hex_dump(rx, len, 32, "RX"); in transfer()
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dcast6-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast6 Cipher 8-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
8 * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
13 #include "glue_helper-asm-avx.S"
15 .file "cast6-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 8-way AVX cast6
47 #define RX %xmm8 macro
126 F_head(b1, RX, RGI1, RGI2, op0); \
[all …]
Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 16-way AVX cast5
46 #define RX %xmm8 macro
126 F_head(b1, RX, RGI1, RGI2, op0); \
127 F_head(b2, RX, RGI3, RGI4, op0); \
129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
14 NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
15 input imaging devices.
[all …]
/kernel/linux/linux-6.6/arch/x86/crypto/
Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 16-way AVX cast5
46 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
131 F_head(b2, RX, RGI3, RGI4, op0); \
133 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
[all …]
Dcast6-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast6 Cipher 8-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
8 * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
13 #include "glue_helper-asm-avx.S"
15 .file "cast6-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 8-way AVX cast6
47 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
35 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
51 #define MCFUART_UIPR 0x34 /* Input Port (r) */
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
61 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
107 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
[all …]
/kernel/linux/linux-6.6/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
35 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
51 #define MCFUART_UIPR 0x34 /* Input Port (r) */
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
61 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
107 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/modules/hdcp/
Dhdcp1_transition.c30 struct mod_hdcp_transition_input_hdcp1 *input, in mod_hdcp_hdcp1_transition() argument
34 struct mod_hdcp_connection *conn = &hdcp->connection; in mod_hdcp_hdcp1_transition()
35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition()
39 if (input->bksv_read != PASS || input->bcaps_read != PASS) { in mod_hdcp_hdcp1_transition()
40 /* 1A-04: repeatedly attempts on port access failure */ in mod_hdcp_hdcp1_transition()
49 if (input->create_session != PASS) { in mod_hdcp_hdcp1_transition()
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
54 } else if (input->an_write != PASS || in mod_hdcp_hdcp1_transition()
55 input->aksv_write != PASS || in mod_hdcp_hdcp1_transition()
56 input->bksv_read != PASS || in mod_hdcp_hdcp1_transition()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/modules/hdcp/
Dhdcp1_transition.c30 struct mod_hdcp_transition_input_hdcp1 *input, in mod_hdcp_hdcp1_transition() argument
34 struct mod_hdcp_connection *conn = &hdcp->connection; in mod_hdcp_hdcp1_transition()
35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition()
39 if (input->bksv_read != PASS || input->bcaps_read != PASS) { in mod_hdcp_hdcp1_transition()
40 /* 1A-04: repeatedly attempts on port access failure */ in mod_hdcp_hdcp1_transition()
49 if (input->create_session != PASS) { in mod_hdcp_hdcp1_transition()
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
54 } else if (input->an_write != PASS || in mod_hdcp_hdcp1_transition()
55 input->aksv_write != PASS || in mod_hdcp_hdcp1_transition()
56 input->bksv_read != PASS || in mod_hdcp_hdcp1_transition()
[all …]
/kernel/linux/linux-6.6/drivers/net/wan/
Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
68 #define RXS 0x16 /* RX Clock Source */
72 #define RRC 0x1A /* RX Ready Control */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
[all …]
/kernel/linux/linux-5.10/drivers/net/wan/
Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
68 #define RXS 0x16 /* RX Clock Source */
72 #define RRC 0x1A /* RX Ready Control */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/
Dsystem_global.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
18 * - Device instances supporting a subset of the class capabilities are
25 * N.B. the 3 input formatters are of 2 different classess
28 /* per-frame parameter handling support */
43 * the bus for too long; as the input system can only buffer
44 * 2 lines on Moorefield and Cherrytrail, the input system buffers
131 IRQ1_ID, /* Input formatter */
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/
Dsystem_global.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
18 * - Device instances supporting a subset of the class capabilities are
25 * N.B. the 3 input formatters are of 2 different classess
40 * the bus for too long; as the input system can only buffer
41 * 2 lines on Moorefield and Cherrytrail, the input system buffers
128 IRQ1_ID, /* Input formatter */
129 IRQ2_ID, /* input system */
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cobalt/
Dcobalt-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from ivtv-ioctl.c and cx18-fileops.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/dma-mapping.h>
15 #include <linux/v4l2-dv-timings.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-event.h>
19 #include <media/v4l2-dv-timings.h>
23 #include "cobalt-alsa.h"
24 #include "cobalt-cpld.h"
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/cobalt/
Dcobalt-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Derived from ivtv-ioctl.c and cx18-fileops.c
7 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/dma-mapping.h>
15 #include <linux/v4l2-dv-timings.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-event.h>
19 #include <media/v4l2-dv-timings.h>
23 #include "cobalt-alsa.h"
24 #include "cobalt-cpld.h"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Datmel-usart.txt4 - compatible: Should be one of the following:
5 - "atmel,at91rm9200-usart"
6 - "atmel,at91sam9260-usart"
7 - "microchip,sam9x60-usart"
8 - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"
9 - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
10 - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart"
11 - reg: Should contain registers location and length
12 - interrupts: Should contain interrupt
13 - clock-names: tuple listing input clock names.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/i2c/
Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
[all …]

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