| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/ |
| D | nvidia,tegra-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
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| D | ceva,ahci-1v84.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Piyush Mehta <piyush.mehta@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
21 const: ceva,ahci-1v84
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | nvidia,tegra124-ahci.txt | 1 Tegra SoC SATA AHCI controller
4 - compatible : Must be one of:
5 - Tegra124 : "nvidia,tegra124-ahci"
6 - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
7 - Tegra210 : "nvidia,tegra210-ahci"
8 - reg : Should contain 2 entries:
9 - AHCI register set (SATA BAR5)
10 - SATA register set
11 - interrupts : Defines the interrupt used by SATA
12 - clocks : Must contain an entry for each entry in clock-names.
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| D | ahci-ceva.txt | 1 Binding for CEVA AHCI SATA Controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
6 - clocks: Input clock specifier. Refer to common clock bindings.
7 - interrupts: Interrupt specifier. Refer to interrupt binding.
8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
11 ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
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| /kernel/linux/linux-6.6/drivers/scsi/isci/ |
| D | phy.c | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
72 /* Maximum arbitration wait time in micro-seconds */
77 return iphy->max_negotiated_speed; in sci_phy_linkrate()
82 struct isci_phy *table = iphy - iphy->phy_index; in phy_to_host()
90 return &phy_to_host(iphy)->pdev->dev; in sciphy_to_dev()
99 iphy->transport_layer_registers = reg; in sci_phy_transport_layer_initialization()
102 &iphy->transport_layer_registers->stp_rni); in sci_phy_transport_layer_initialization()
108 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
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| D | phy.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
63 /* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
71 /* This is the timeout for the SATA OOB/SN because the hardware does not
72 * recognize a hot plug after OOB signal but before the SN signals. We need to
74 * notification from the hardware that we restart the hardware OOB state
80 * isci_phy - hba local phy infrastructure
83 * @phy_index: physical index relative to the controller (0-3)
85 * @sata_timer: timeout SATA signature FIS arrival
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| /kernel/linux/linux-5.10/drivers/scsi/isci/ |
| D | phy.c | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
72 /* Maximum arbitration wait time in micro-seconds */
77 return iphy->max_negotiated_speed; in sci_phy_linkrate()
82 struct isci_phy *table = iphy - iphy->phy_index; in phy_to_host()
90 return &phy_to_host(iphy)->pdev->dev; in sciphy_to_dev()
99 iphy->transport_layer_registers = reg; in sci_phy_transport_layer_initialization()
102 &iphy->transport_layer_registers->stp_rni); in sci_phy_transport_layer_initialization()
108 tl_control = readl(&iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization()
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| D | phy.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
63 /* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
71 /* This is the timeout for the SATA OOB/SN because the hardware does not
72 * recognize a hot plug after OOB signal but before the SN signals. We need to
74 * notification from the hardware that we restart the hardware OOB state
80 * isci_phy - hba local phy infrastructure
83 * @phy_index: physical index relative to the controller (0-3)
85 * @sata_timer: timeout SATA signature FIS arrival
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| /kernel/linux/linux-6.6/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
77 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /kernel/linux/linux-5.10/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
76 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | ahci_ceva.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * CEVA AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
72 #define DRV_NAME "ahci-ceva"
77 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
123 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
124 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
141 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()
149 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()
162 /* Phy Control OOB timing parameters COMINIT */ in ahci_ceva_setup()
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| D | ahci_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DRV_NAME "tegra-ahci"
179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
205 val = readl(tegra->sata_regs + in tegra124_ahci_init()
211 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra124_ahci_init()
[all …]
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| /kernel/linux/linux-6.6/drivers/ata/ |
| D | ahci_ceva.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * CEVA AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
142 * Set Mem Addr Read ID, Write ID for non-data transfers in ahci_ceva_setup()
150 if (cevapriv->is_cci_enabled) { in ahci_ceva_setup()
163 /* Phy Control OOB timing parameters COMINIT */ in ahci_ceva_setup()
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| D | ahci_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DRV_NAME "tegra-ahci"
184 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()
187 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
196 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()
208 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
210 val = readl(tegra->sata_regs + in tegra124_ahci_init()
216 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra124_ahci_init()
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| /kernel/linux/linux-5.10/Documentation/scsi/ |
| D | libsas.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 phy/OOB/link management, the SAS layer is concerned with:
20 (SATA), and
25 phy/OOB management, and vendor specific tasks and generates
40 start OOB (at which point your driver will start calling the
47 ------------------
75 - must be set (0/1)
78 - must be set [0,MAX_PHYS)]
81 - must be set
84 - you set this when OOB has finished and then notify
[all …]
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| /kernel/linux/linux-6.6/Documentation/scsi/ |
| D | libsas.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 phy/OOB/link management, the SAS layer is concerned with:
20 (SATA), and
25 phy/OOB management, and vendor specific tasks and generates
40 start OOB (at which point your driver will start calling the
47 ------------------
75 - must be set (0/1)
78 - must be set [0,MAX_PHYS)]
81 - must be set
84 - you set this when OOB has finished and then notify
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1232-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
26 stdout-path = "serial0:115200n8";
39 &sata {
41 /* SATA OOB timing settings */
42 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
43 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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| D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP zc1751-xm015-dc1 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
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| D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm017-dc3 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
75 phy-mode = "rgmii-id";
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| D | zynqmp-zcu104-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
51 phy-handle = <&phy0>;
52 phy-mode = "rgmii-id";
53 phy0: ethernet-phy@c {
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1232-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
45 #size-cells = <1>;
47 spi-tx-bus-width = <4>;
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| D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
43 compatible = "fixed-clock";
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| D | zynqmp-sck-kv-g-revA.dtso | 1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-brcm-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
191 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
194 switch (priv->version) { in brcm_sata_ctrl_base()
199 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
203 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
209 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
210 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
213 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
214 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
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| /kernel/linux/linux-6.6/drivers/phy/broadcom/ |
| D | phy-brcm-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* The older SATA PHY registers duplicated per port registers within the map,
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
[all …]
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