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/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
9 #include <linux/clk-provider.h>
13 #include "clk-scu.h"
21 * struct clk_scu - Description of one SCU clock
23 * @rsrc_id: resource ID of this SCU clock
33 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
34 * @hdr: SCU protocol header
37 * @clk: clk type of this resource
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-cpu.o
8 mxc-clk-objs += clk-divider-gate.o
9 mxc-clk-objs += clk-fixup-div.o
10 mxc-clk-objs += clk-fixup-mux.o
11 mxc-clk-objs += clk-frac-pll.o
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
44 * @rsrc_id: resource ID of this SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
62 * @rsrc_id: resource ID of this SCU clock
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dfsl,scu-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
[all …]
Dairoha,en7523-scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felix Fietkau <nbd@nbd.name>
11 - John Crispin <nbd@nbd.name>
25 [1]: <include/dt-bindings/clock/en7523-clk.h>.
32 - const: airoha,en7523-scu
37 "#clock-cells":
44 - compatible
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
19 The scu node with the following properties shall be under the /firmware/ node.
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
60 i.MX SCU Client Device Node:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/aspeed/
Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
5 #include <linux/dma-mapping.h>
61 u32 dac_reg; /* DAC register in SCU */
63 u32 vga_scratch_reg; /* VGA scratch register in SCU */
93 { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
94 { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
95 { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
114 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
115 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
[all …]
/kernel/linux/linux-6.6/drivers/soc/aspeed/
Daspeed-lpc-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk.h>
17 #include <linux/aspeed-lpc-ctrl.h>
19 #define DEVICE_NAME "aspeed-lpc-ctrl"
34 struct clk *clk; member
40 struct regmap *scu; member
45 return container_of(file->private_data, struct aspeed_lpc_ctrl, in file_aspeed_lpc_ctrl()
52 unsigned long vsize = vma->vm_end - vma->vm_start; in aspeed_lpc_ctrl_mmap()
53 pgprot_t prot = vma->vm_page_prot; in aspeed_lpc_ctrl_mmap()
55 if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT) in aspeed_lpc_ctrl_mmap()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/aspeed/
Daspeed_gfx_drv.c1 // SPDX-License-Identifier: GPL-2.0+
4 #include <linux/clk.h>
5 #include <linux/dma-mapping.h>
74 drm->mode_config.min_width = 0; in aspeed_gfx_setup_mode_config()
75 drm->mode_config.min_height = 0; in aspeed_gfx_setup_mode_config()
76 drm->mode_config.max_width = 800; in aspeed_gfx_setup_mode_config()
77 drm->mode_config.max_height = 600; in aspeed_gfx_setup_mode_config()
78 drm->mode_config.funcs = &aspeed_gfx_mode_config_funcs; in aspeed_gfx_setup_mode_config()
89 reg = readl(priv->base + CRT_CTRL1); in aspeed_gfx_irq_handler()
92 drm_crtc_handle_vblank(&priv->pipe.crtc); in aspeed_gfx_irq_handler()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/apm/
Dscu.txt1 APM X-GENE SoC series SCU Registers
7 - compatible : should contain two values. First value must be:
8 - "apm,xgene-scu"
11 - reg : offset and length of the register set.
14 scu: system-clk-controller@17000000 {
15 compatible = "apm,xgene-scu","syscon";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/apm/
Dscu.txt1 APM X-GENE SoC series SCU Registers
7 - compatible : should contain two values. First value must be:
8 - "apm,xgene-scu"
11 - reg : offset and length of the register set.
14 scu: system-clk-controller@17000000 {
15 compatible = "apm,xgene-scu","syscon";
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
22 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-lpc18xx.c2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
12 #include <linux/clk.h>
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 /* LPC18XX SCU analog function registers */
32 /* LPC18XX SCU pin register definitions */
54 /* LPC18XX SCU pin interrupt select registers */
68 TYPE_ND, /* Normal-drive */
69 TYPE_HD, /* High-drive */
70 TYPE_HS, /* High-speed */
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-lpc18xx.c2 * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
12 #include <linux/clk.h>
19 #include <linux/pinctrl/pinconf-generic.h>
22 #include "pinctrl-utils.h"
24 /* LPC18XX SCU analog function registers */
30 /* LPC18XX SCU pin register definitions */
52 /* LPC18XX SCU pin interrupt select registers */
66 TYPE_ND, /* Normal-drive */
67 TYPE_HD, /* High-drive */
68 TYPE_HS, /* High-speed */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx93-flexcan
21 - fsl,imx8qm-flexcan
22 - fsl,imx8mp-flexcan
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0019_linux_drivers_gpio.patch7 Change-Id: I85874db4979e1d5dcfde13a3ecaeca8507d0ea43
9 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
11 --- a/drivers/gpio/Kconfig
13 @@ -427,6 +427,12 @@ config GPIO_MXC
26 @@ -434,6 +440,13 @@ config GPIO_MXS
40 @@ -628,7 +641,7 @@ config GPIO_UNIPHIER
44 - depends on ARCH_MXC && SOC_VF610
49 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
51 --- a/drivers/gpio/Makefile
53 @@ -129,6 +129,7 @@ obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
[all …]
D0015_linux_drivers_clk.patch7 Change-Id: Iad3fba6c51f290df25555d1136fd2cc4761d3324
9 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
11 --- a/drivers/clk/Kconfig
12 +++ b/drivers/clk/Kconfig
13 @@ -374,6 +374,7 @@ source "drivers/clk/mvebu/Kconfig"
14 source "drivers/clk/qcom/Kconfig"
15 source "drivers/clk/renesas/Kconfig"
16 source "drivers/clk/rockchip/Kconfig"
17 +source "drivers/clk/s32/Kconfig"
18 source "drivers/clk/samsung/Kconfig"
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]
/kernel/linux/linux-6.6/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
[all …]

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