Home
last modified time | relevance | path

Searched +full:scu +full:- +full:pd (Results 1 – 25 of 37) sorted by relevance

12

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/
Dfsl,scu-pd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,scu-pd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Power Domain Based on SCU Message Protocol
10 - Dong Aisheng <aisheng.dong@nxp.com>
12 description: i.MX SCU Client Device Node
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
14 Power domain bindings based on SCU Message Protocol
17 - $ref: power-domain.yaml#
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
19 The scu node with the following properties shall be under the /firmware/ node.
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
60 i.MX SCU Client Device Node:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
[all …]
/kernel/linux/linux-5.10/drivers/firmware/imx/
Dscu-pd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 * Implementation of the SCU based Power Domains
10 * single global power domain and implement the ->attach|detach_dev()
12 * From within the ->attach_dev(), we could get the OF node for
13 * the device that is being attached and then parse the power-domain
18 * Additionally, we need to implement the ->stop() and ->start()
20 * rather than using the above ->power_on|off() callbacks.
23 * 1. The ->attach_dev() of power domain infrastructure still does
25 * in is a virtual PD device, it does not help for parsing the real
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IMX_DSP) += imx-dsp.o
3 obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o rm.o imx-scu-soc.o
4 obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/pmdomain/imx/
Dscu-pd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
7 * Implementation of the SCU based Power Domains
10 * single global power domain and implement the ->attach|detach_dev()
12 * From within the ->attach_dev(), we could get the OF node for
13 * the device that is being attached and then parse the power-domain
18 * Additionally, we need to implement the ->stop() and ->start()
20 * rather than using the above ->power_on|off() callbacks.
23 * 1. The ->attach_dev() of power domain infrastructure still does
25 * in is a virtual PD device, it does not help for parsing the real
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
3 obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
4 obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o
5 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o
6 obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o
7 obj-$(CONFIG_SOC_IMX9) += imx93-pd.o
8 obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o
/kernel/linux/linux-6.6/arch/arm/mach-rockchip/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 static int pmu_power_domain_is_on(int pd) in pmu_power_domain_is_on() argument
47 return !(val & BIT(pd)); in pmu_power_domain_is_on()
57 np = dev->of_node; in rockchip_get_core_reset()
64 static int pmu_set_power_domain(int pd, bool on) in pmu_set_power_domain() argument
66 u32 val = (on) ? 0 : BIT(pd); in pmu_set_power_domain()
67 struct reset_control *rstc = rockchip_get_core_reset(pd); in pmu_set_power_domain()
72 __func__, pd); in pmu_set_power_domain()
85 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); in pmu_set_power_domain()
92 ret = -1; in pmu_set_power_domain()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-rockchip/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 static int pmu_power_domain_is_on(int pd) in pmu_power_domain_is_on() argument
47 return !(val & BIT(pd)); in pmu_power_domain_is_on()
57 np = dev->of_node; in rockchip_get_core_reset()
64 static int pmu_set_power_domain(int pd, bool on) in pmu_set_power_domain() argument
66 u32 val = (on) ? 0 : BIT(pd); in pmu_set_power_domain()
67 struct reset_control *rstc = rockchip_get_core_reset(pd); in pmu_set_power_domain()
72 __func__, pd); in pmu_set_power_domain()
85 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); in pmu_set_power_domain()
92 ret = -1; in pmu_set_power_domain()
[all …]
/kernel/linux/linux-5.10/drivers/soc/renesas/
Dr8a779a0-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car V3U System Controller
22 #include <dt-bindings/power/r8a779a0-sysc.h>
28 #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
32 #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
40 int parent; /* -1 if none */
45 * SoC-specific Power Area Description
53 { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
68 { "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
69 { "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
[all …]
Drcar-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car SYSC Power management support
6 * Copyright (C) 2015-2017 Glider bvba
18 #include <linux/soc/renesas/rcar-sysc.h>
20 #include "rcar-sysc.h"
36 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
37 * Use PSCI on R-Car Gen3
56 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
89 return -EAGAIN; in rcar_sysc_pwr_on_off()
92 iowrite32(BIT(sysc_ch->chan_bit), in rcar_sysc_pwr_on_off()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dimx8dxl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
Dimx8qm.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
/kernel/linux/linux-6.6/drivers/pmdomain/renesas/
Drcar-gen4-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 SYSC Power management support
22 #include "rcar-gen4-sysc.h"
26 #define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
27 #define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
39 #define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */
45 #define PDRSR_OFF BIT(0) /* Power-OFF state */
46 #define PDRSR_ON BIT(4) /* Power-ON state */
47 #define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */
48 #define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */
[all …]
Drcar-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car SYSC Power management support
6 * Copyright (C) 2015-2017 Glider bvba
19 #include <linux/soc/renesas/rcar-sysc.h>
21 #include "rcar-sysc.h"
37 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
38 * Use PSCI on R-Car Gen3
57 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
88 return -EAGAIN; in rcar_sysc_pwr_on_off()
91 iowrite32(BIT(sysc_ch->chan_bit), in rcar_sysc_pwr_on_off()
[all …]
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0018_linux_drivers_firmware.patch7 Change-Id: I36b7f7c1c8a25ed6657505008ad1251ef7273f99
9 diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h
11 --- a/drivers/firmware/arm_scmi/common.h
13 @@ -169,6 +169,7 @@ DECLARE_SCMI_REGISTER_UNREGISTER(perf);
21 diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c
23 --- a/drivers/firmware/arm_scmi/smc.c
25 @@ -9,9 +9,11 @@
26 #include <linux/arm-smccc.h>
37 @@ -23,6 +25,8 @@
46 @@ -30,8 +34,19 @@ struct scmi_smc {
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-scu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
42 * struct clk_scu - Description of one SCU clock
44 * @rsrc_id: resource ID of this SCU clock
60 * struct clk_gpr_scu - Description of one SCU GPR clock
62 * @rsrc_id: resource ID of this SCU clock
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
18 by the SCU resources and clock controls. Thus even if the clock is
24 include/dt-bindings/clock/imx8-clock.h
29 - fsl,imx8qxp-lpcg-adma
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
18 by the SCU resources and clock controls. Thus even if the clock is
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
25 const: fsl,imx8qxp-pxl2dpi
27 fsl,sc-resource:
29 description: The SCU resource ID associated with this PXL2DPI instance.
[all …]

12