Home
last modified time | relevance | path

Searched +full:sec +full:- +full:era (Results 1 – 25 of 54) sorted by relevance

123

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/
Dfsl-sec6.txt1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
[all …]
Dfsl,sec-v4.0.yaml1 # SPDX-License-Identifier: GPL-2.0
2 # Copyright (C) 2008-2011 Freescale Semiconductor Inc.
4 ---
5 $id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Freescale SEC 4
11 - '"Horia Geantă" <horia.geanta@nxp.com>'
12 - Pankaj Gupta <pankaj.gupta@nxp.com>
13 - Gaurav Jain <gaurav.jain@nxp.com>
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dfsl-sec6.txt1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
5 -Job Ring Node
6 -Full Example
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
[all …]
Dfsl-sec4.txt2 SEC 4 Device Tree Binding
3 Copyright (C) 2008-2011 Freescale Semiconductor Inc.
6 -Overview
7 -SEC 4 Node
8 -Job Ring Node
9 -Run Time Integrity Check (RTIC) Node
10 -Run Time Integrity Check (RTIC) Memory Node
11 -Secure Non-Volatile Storage (SNVS) Node
12 -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
13 -Full Example
[all …]
/kernel/linux/linux-5.10/drivers/crypto/caam/
Dcaamalg_desc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2016-2019 NXP
14 * both of which are specified in req->src and req->dst
45 * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor
46 * (non-protocol) with no (null) encryption.
49 * A split key is required for SEC Era < 6; the size of the split key
50 * is specified in this case. Valid algorithm values - one of
54 * @era: SEC Era
57 unsigned int icvsize, int era) in cnstr_shdsc_aead_null_encap() argument
66 if (era < 6) { in cnstr_shdsc_aead_null_encap()
[all …]
Dcaamhash_desc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2017-2019 NXP
13 * cnstr_shdsc_ahash - ahash shared descriptor
16 * A split key is required for SEC Era < 6; the size of the split key
18 * Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
26 * @era: SEC Era
29 int digestsize, int ctx_len, bool import_ctx, int era) in cnstr_shdsc_ahash() argument
31 u32 op = adata->algtype; in cnstr_shdsc_ahash()
36 if (state != OP_ALG_AS_UPDATE && adata->keylen) { in cnstr_shdsc_ahash()
43 if (era < 6) in cnstr_shdsc_ahash()
[all …]
Dctrl.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019 NXP
44 /* INIT RNG in non-test mode */ in build_instantiation_desc()
83 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
85 * @ctrldev - pointer to device
86 * @status - descriptor status, after being run
88 * Return: - 0 if no error occurred
[all …]
Ddpseci.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
10 * Data Path SEC Interface API
28 #define DPSECI_ALL_QUEUES (u8)(-1)
41 * struct dpseci_cfg - Structure representing DPSECI configuration
44 * @num_tx_queues: num of queues towards the SEC
45 * @num_rx_queues: num of queues back from the SEC
46 * @priorities: Priorities for the SEC hardware processing;
48 * towards the SEC;
[all …]
Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM/SEC 4.x driver backend
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
31 * Storage for tracking each in-process entry moving across a ring
42 /* Private sub-storage for a single JobR */
61 * DMA-safe */
64 void *outring; /* Base of output ring, DMA-safe */
69 * Driver-private storage for a single CAAM block instance
72 /* Physical-presence section */
[all …]
/kernel/linux/linux-6.6/drivers/crypto/caam/
Dcaamalg_desc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2016-2019 NXP
14 * both of which are specified in req->src and req->dst
45 * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor
46 * (non-protocol) with no (null) encryption.
49 * A split key is required for SEC Era < 6; the size of the split key
50 * is specified in this case. Valid algorithm values - one of
54 * @era: SEC Era
57 unsigned int icvsize, int era) in cnstr_shdsc_aead_null_encap() argument
66 if (era < 6) { in cnstr_shdsc_aead_null_encap()
[all …]
Dcaamhash_desc.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2017-2019 NXP
13 * cnstr_shdsc_ahash - ahash shared descriptor
16 * A split key is required for SEC Era < 6; the size of the split key
18 * Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
26 * @era: SEC Era
29 int digestsize, int ctx_len, bool import_ctx, int era) in cnstr_shdsc_ahash() argument
31 u32 op = adata->algtype; in cnstr_shdsc_ahash()
36 if (state != OP_ALG_AS_UPDATE && adata->keylen) { in cnstr_shdsc_ahash()
43 if (era < 6) in cnstr_shdsc_ahash()
[all …]
Ddpseci.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
10 * Data Path SEC Interface API
28 #define DPSECI_ALL_QUEUES (u8)(-1)
41 * struct dpseci_cfg - Structure representing DPSECI configuration
44 * @num_tx_queues: num of queues towards the SEC
45 * @num_rx_queues: num of queues back from the SEC
46 * @priorities: Priorities for the SEC hardware processing;
48 * towards the SEC;
[all …]
Dctrl.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
45 /* INIT RNG in non-test mode */ in build_instantiation_desc()
93 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
95 * @ctrldev - pointer to device
96 * @status - descriptor status, after being run
98 * Return: - 0 if no error occurred
[all …]
Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM/SEC 4.x driver backend
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
39 * Storage for tracking each in-process entry moving across a ring
60 /* Private sub-storage for a single JobR */
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dqoriq-sec6.0-0.dtsi2 * QorIQ Sec/Crypto 6.0 device tree stub
35 compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
36 "fsl,sec-v4.0";
37 fsl,sec-era = <6>;
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "fsl,sec-v6.0-job-ring",
43 "fsl,sec-v5.2-job-ring",
44 "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.4-job-ring",
[all …]
Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.0-job-ring";
69 compatible = "fsl,sec-v4.0-rtic";
[all …]
Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v4.2-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v4.2-job-ring",
[all …]
Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v5.0-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v5.0-job-ring",
[all …]
Dqoriq-sec5.2-0.dtsi2 * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.2-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
53 compatible = "fsl,sec-v5.2-job-ring",
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dqoriq-sec6.0-0.dtsi2 * QorIQ Sec/Crypto 6.0 device tree stub
35 compatible = "fsl,sec-v6.0", "fsl,sec-v5.0",
36 "fsl,sec-v4.0";
37 fsl,sec-era = <6>;
38 #address-cells = <1>;
39 #size-cells = <1>;
42 compatible = "fsl,sec-v6.0-job-ring",
43 "fsl,sec-v5.2-job-ring",
44 "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.4-job-ring",
[all …]
Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
Dqoriq-sec4.0-0.dtsi2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.0-job-ring";
51 compatible = "fsl,sec-v4.0-job-ring";
57 compatible = "fsl,sec-v4.0-job-ring";
63 compatible = "fsl,sec-v4.0-job-ring";
69 compatible = "fsl,sec-v4.0-rtic";
[all …]
Dqoriq-sec5.0-0.dtsi2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v5.0-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v5.0-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v5.0-job-ring",
[all …]
Dqoriq-sec4.2-0.dtsi2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
38 #address-cells = <1>;
39 #size-cells = <1>;
45 compatible = "fsl,sec-v4.2-job-ring",
46 "fsl,sec-v4.0-job-ring";
52 compatible = "fsl,sec-v4.2-job-ring",
53 "fsl,sec-v4.0-job-ring";
59 compatible = "fsl,sec-v4.2-job-ring",
[all …]

123