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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-bcm/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
106 return -EINVAL; in nsp_write_lut()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-bcm/
Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
106 return -EINVAL; in nsp_write_lut()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm-nsp-ax.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar Plus Ax stepping-specific bindings.
4 * Notable differences from B0+ are the secondary-boot-reg and
9 secondary-boot-reg = <0xffff042c>;
13 /delete-property/ dma-coherent;
17 /delete-property/ dma-coherent;
21 /delete-property/ dma-coherent;
25 /delete-property/ dma-coherent;
29 /delete-property/ dma-coherent;
33 /delete-property/ dma-coherent;
[all …]
Dbcm23550.dtsi34 #include <dt-bindings/clock/bcm21664.h>
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/interrupt-controller/irq.h>
39 #address-cells = <1>;
40 #size-cells = <1>;
43 interrupt-parent = <&gic>;
46 #address-cells = <1>;
47 #size-cells = <0>;
51 compatible = "arm,cortex-a7";
52 reg = <0>;
[all …]
Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
/kernel/linux/linux-5.10/arch/arm64/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
62 * so we need some other way of telling a new secondary core
92 return -ENOSYS; in op_cpu_kill()
98 * Boot a secondary CPU, and assign it the specified idle task.
105 if (ops->cpu_boot) in boot_secondary()
106 return ops->cpu_boot(cpu); in boot_secondary()
108 return -EOPNOTSUPP; in boot_secondary()
119 * We need to tell the secondary core where to find its stack and the in __cpu_up()
130 pr_err("CPU%u: failed to boot: %d\n", cpu, ret); in __cpu_up()
[all …]
Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mstar/
Dmstar,smpctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Palmer <daniel@thingy.jp>
15 have a region of registers that allow setting the boot address
16 and a magic number that allows secondary processors to leave
17 the loop they are parked in by the boot ROM.
22 - enum:
23 - sstar,ssd201-smpctrl # SSD201/SSD202D
24 - const: mstar,smpctrl
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
61 * so we need some other way of telling a new secondary core
91 return -ENOSYS; in op_cpu_kill()
97 * Boot a secondary CPU, and assign it the specified idle task.
104 if (ops->cpu_boot) in boot_secondary()
105 return ops->cpu_boot(cpu); in boot_secondary()
107 return -EOPNOTSUPP; in boot_secondary()
118 * We need to tell the secondary core where to find its stack and the in __cpu_up()
127 pr_err("CPU%u: failed to boot: %d\n", cpu, ret); in __cpu_up()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/openrisc/opencores/
Dor1ksim.txt6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/openrisc/opencores/
Dor1ksim.txt6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm23550.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
37 #include "dt-bindings/clock/bcm21664.h"
40 #address-cells = <1>;
41 #size-cells = <1>;
44 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a7";
53 reg = <0>;
[all …]
Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
[all …]

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