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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dusb251xb.txt1 Microchip USB 2.0 Hi-Speed Hub Controller
4 Hi-Speed Controller.
7 - compatible : Should be "microchip,usb251xb" or one of the specific types:
11 - reg : I2C address on the selected bus (default is <0x2C>)
14 - reset-gpios : Should specify the gpio for hub reset
15 - vdd-supply : Should specify the phandle to the regulator supplying vdd
16 - skip-config : Skip Hub configuration, but only send the USB-Attach command
17 - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424)
18 - product-id : Set USB Product ID of the hub (16 bit, default depends on type)
19 - device-id : Set USB Device ID of the hub (16 bit, default is 0x0bb3)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dusb251xb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
[all …]
/kernel/linux/linux-6.6/include/soc/at91/
Dsama7-ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
[all …]
Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68 #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "F…
69 #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "…
73 #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
[all …]
/kernel/linux/linux-6.6/tools/crypto/ccp/
Dtest_dbc.py2 # SPDX-License-Identifier: GPL-2.0
25 def system_is_secured() -> bool:
34 def __init__(self, data) -> None: argument
35 self.d = None
36 self.signature = b"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
37 self.uid = b"1111111111111111"
40 def setUp(self) -> None: argument
41 self.d = open(DEVICE_NODE)
44 def tearDown(self) -> None: argument
45 if self.d:
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/kernel/linux/linux-5.10/scripts/gdb/linux/
Dgenpd.py1 # SPDX-License-Identifier: GPL-2.0
25 if dev['power']['runtime_error']:
27 if dev['power']['disable_depth']:
35 return _RPM_STATUS_LOOKUP[dev['power']['runtime_status']]
43 def __init__(self): argument
44 super(LxGenPDSummary, self).__init__('lx-genpd-summary', gdb.COMMAND_DATA)
46 def summary_one(self, genpd): argument
50 status_string = 'off-{}'.format(genpd['state_idx'])
59 gdb.write('%-30s %-15s %s\n' % (
70 gdb.write(' %-50s %s\n' % (kobj_path, rtpm_status_str(dev)))
[all …]
/kernel/linux/linux-6.6/scripts/gdb/linux/
Dgenpd.py1 # SPDX-License-Identifier: GPL-2.0
25 if dev['power']['runtime_error']:
27 if dev['power']['disable_depth']:
35 return _RPM_STATUS_LOOKUP[dev['power']['runtime_status']]
43 def __init__(self): argument
44 super(LxGenPDSummary, self).__init__('lx-genpd-summary', gdb.COMMAND_DATA)
46 def summary_one(self, genpd): argument
50 status_string = 'off-{}'.format(genpd['state_idx'])
59 gdb.write('%-30s %-15s %s\n' % (
70 gdb.write(' %-50s %s\n' % (kobj_path, rtpm_status_str(dev)))
[all …]
/kernel/linux/linux-6.6/drivers/usb/host/
Dohci-omap.c1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2005 David Brownell
7 * (C) Copyright 2002 Hewlett-Packard Company
13 * and on ohci-sa1111.c by Christopher Hoover <ch@hpl.hp.com>
19 #include <linux/dma-mapping.h>
28 #include <linux/platform_data/usb-omap1.h>
29 #include <linux/soc/ti/omap1-usb.h>
30 #include <linux/soc/ti/omap1-mux.h>
31 #include <linux/soc/ti/omap1-soc.h>
32 #include <linux/soc/ti/omap1-io.h>
[all …]
Dohci-s3c2410.c1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * (C) Copyright 2002 Hewlett-Packard Company
14 * Modified for S3C2410 from ohci-sa1111.c, ohci-omap.c and ohci-lh7a40.c
28 #include <linux/platform_data/usb-ohci-s3c2410.h>
55 return dev_get_platdata(hcd->self.controller); in to_s3c2410_info()
60 struct s3c2410_hcd_info *info = dev_get_platdata(&dev->dev); in s3c2410_start_hc()
62 dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); in s3c2410_start_hc()
70 info->hcd = hcd; in s3c2410_start_hc()
71 info->report_oc = s3c2410_hcd_oc; in s3c2410_start_hc()
[all …]
/kernel/linux/linux-5.10/drivers/usb/host/
Dohci-omap.c1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2005 David Brownell
7 * (C) Copyright 2002 Hewlett-Packard Company
13 * and on ohci-sa1111.c by Christopher Hoover <ch@hpl.hp.com>
19 #include <linux/dma-mapping.h>
35 #include <asm/mach-types.h>
43 /* OMAP-1510 OHCI has its own MMU for DMA */
59 struct gpio_desc *power; member
63 static const char hcd_name[] = "ohci-omap";
67 ((struct ohci_omap_priv *)hcd_to_ohci(h)->priv)
[all …]
Dohci-s3c2410.c1 // SPDX-License-Identifier: GPL-1.0+
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * (C) Copyright 2002 Hewlett-Packard Company
14 * Modified for S3C2410 from ohci-sa1111.c, ohci-omap.c and ohci-lh7a40.c
28 #include <linux/platform_data/usb-ohci-s3c2410.h>
42 static const char hcd_name[] = "ohci-s3c2410";
57 return dev_get_platdata(hcd->self.controller); in to_s3c2410_info()
62 struct s3c2410_hcd_info *info = dev_get_platdata(&dev->dev); in s3c2410_start_hc()
64 dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); in s3c2410_start_hc()
72 info->hcd = hcd; in s3c2410_start_hc()
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/
Dali_drw.json24 "BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
136 "BriefDescription": "A read-write turnaround.",
150 "BriefDescription": "A Write-After-Read hazard.",
157 "BriefDescription": "A Read-After-Write hazard.",
164 "BriefDescription": "A Write-After-Write hazard.",
171 "BriefDescription": "Rank0 enters self-refresh(SRE).",
178 "BriefDescription": "Rank1 enters self-refresh(SRE).",
185 "BriefDescription": "Rank2 enters self-refresh(SRE).",
192 "BriefDescription": "Rank3 enters self-refresh(SRE).",
199 "BriefDescription": "Rank0 enters power-down(PDE).",
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-socfpga/
Dself-refresh.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
48 /* Enable dynamic clock gating in the Power Control Register. */
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-socfpga/
Dself-refresh.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-2015 Altera Corporation. All rights reserved.
32 .arch armv7-a
44 * return value: lower 16 bits: loop count going into self refresh
45 * upper 16 bits: loop count exiting self refresh
48 /* Enable dynamic clock gating in the Power Control Register. */
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
109 * Shift loop count for exiting self refresh into upper 16 bits.
110 * Leave loop count for requesting self refresh in lower 16 bits.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/
Drk3399_dmc.txt4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
7 rockchip-dfi.txt
8 - clocks: Phandles for clock specified in "clock-names" property
9 - clock-names : The name of clock used by the DFI, must be
11 - operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
13 - center-supply: DMC supply node.
14 - status: Marks the node enabled/disabled.
17 - interrupts: The CPU interrupt number. The interrupt specifier
21 - rockchip,pmu: Phandle to the syscon managing the "PMU general register
[all …]
/kernel/linux/linux-5.10/include/soc/at91/
Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68 #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "F…
69 #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "…
73 #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-at91/
Dpm_suspend.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
91 * Set state for 2.5V low power regulator
92 * @ena: 0 - disable regulator
93 * 1 - enable regulator
125 * Enable self-refresh
164 /* Switch to self-refresh. */
170 /* Wait for self-refresh enter. */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-lpc32xx/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
12 * LPC32XX CPU and system power management
14 * The LPC32XX has three CPU modes for controlling system power: run,
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
25 * Direct-run mode:
36 * wake the system up back into direct-run mode.
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
42 * a transition to direct-run mode will stop all DDR accesses (no clocks).
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/
Dpm.c2 * arch/arm/mach-lpc32xx/pm.c
14 * LPC32XX CPU and system power management
16 * The LPC32XX has three CPU modes for controlling system power: run,
17 * direct-run, and halt modes. When switching between halt and run modes,
18 * the CPU transistions through direct-run mode. For Linux, direct-run
27 * Direct-run mode:
38 * wake the system up back into direct-run mode.
43 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
44 * a transition to direct-run mode will stop all DDR accesses (no clocks).
45 * Because of this, the code to switch power modes and the code to enter
[all …]
/kernel/linux/linux-5.10/drivers/media/usb/cx231xx/
Dcx231xx-pcb-cfg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 cx231xx-pcb-cfg.h - driver for Conexant
87 Sound-IF Signals present */
93 SELF_POWER = 0x0, /* 0: self power */
94 BUS_POWER = 0x40 /* 1: bus power */
172 u8 type; /* bus power or self power,
173 self power--0, bus_power--1 */
174 u8 speed; /* usb speed, 2.0--1, 1.1--0 */
176 u32 ts1_source; /* three source -- BDA,External,encode */
179 u8 digital_index; /* bus-power used */
[all …]
/kernel/linux/linux-6.6/drivers/media/usb/cx231xx/
Dcx231xx-pcb-cfg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 cx231xx-pcb-cfg.h - driver for Conexant
87 Sound-IF Signals present */
93 SELF_POWER = 0x0, /* 0: self power */
94 BUS_POWER = 0x40 /* 1: bus power */
172 u8 type; /* bus power or self power,
173 self power--0, bus_power--1 */
174 u8 speed; /* usb speed, 2.0--1, 1.1--0 */
176 u32 ts1_source; /* three source -- BDA,External,encode */
179 u8 digital_index; /* bus-power used */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/
Ddrm_self_refresh_helper.c1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
42 * &drm_crtc_state.self_refresh_active if they want to enter low power mode
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/
Ddrm_self_refresh_helper.c1 // SPDX-License-Identifier: MIT
27 * framework to implement panel self refresh (SR) support. Drivers are
31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
32 * (meaning it knows how to initiate self refresh on the panel).
38 * that tells you to disable/enable SR on the panel instead of power-cycling it.
42 * &drm_crtc_state.self_refresh_active if they want to enter low power mode
72 struct drm_crtc *crtc = sr_data->crtc; in drm_self_refresh_helper_entry_work()
73 struct drm_device *dev = crtc->dev; in drm_self_refresh_helper_entry_work()
85 ret = -ENOMEM; in drm_self_refresh_helper_entry_work()
90 state->acquire_ctx = &ctx; in drm_self_refresh_helper_entry_work()
[all …]
/kernel/linux/linux-5.10/drivers/staging/iio/accel/
Dadis16203.c1 // SPDX-License-Identifier: GPL-2.0+
28 /* Output, power supply */
37 /* Output, x-axis inclination */
40 /* Output, y-axis inclination */
64 /* General-purpose digital input/output control */
87 /* Self-test at power-on: 1 = disabled, 0 = enabled */
93 /* Self-test enable */
96 /* Data-ready enable: 1 = enabled, 0 = disabled */
99 /* Data-ready polarity: 1 = active high, 0 = active low */
102 /* Data-ready line selection: 1 = DIO1, 0 = DIO0 */
[all …]

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