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/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
DSpirvShaderImage.cpp77 sw::SIMD::Float sRGBtoLinear(sw::SIMD::Float c) in sRGBtoLinear()
79 sw::SIMD::Float lc = c * sw::SIMD::Float(1.0f / 12.92f); in sRGBtoLinear()
80 …sw::SIMD::Float ec = sw::power((c + sw::SIMD::Float(0.055f)) * sw::SIMD::Float(1.0f / 1.055f), sw:… in sRGBtoLinear()
82 sw::SIMD::Int linear = CmpLT(c, sw::SIMD::Float(0.04045f)); in sRGBtoLinear()
84 …return rr::As<sw::SIMD::Float>((linear & rr::As<sw::SIMD::Int>(lc)) | (~linear & rr::As<sw::SIMD::… in sRGBtoLinear()
313 Array<SIMD::Float> out(4); in EmitImageSample()
328 void SpirvShader::EmitImageSampleUnconditional(Array<SIMD::Float> &out, const ImageInstruction &ins… in EmitImageSampleUnconditional()
362 void SpirvShader::callSamplerFunction(Pointer<Byte> samplerFunction, Array<SIMD::Float> &out, Point… in callSamplerFunction()
364 Array<SIMD::Float> in(16); // Maximum 16 input parameter components. in callSamplerFunction()
424 in[i] = As<SIMD::Float>(SIMD::Int(0)); in callSamplerFunction()
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DSpirvShaderGLSLstd450.cpp27 sw::SIMD::Float Interpolate(const sw::SIMD::Float &x, const sw::SIMD::Float &y, const sw::SIMD::Flo… in Interpolate()
28 … const sw::SIMD::Float &A, const sw::SIMD::Float &B, const sw::SIMD::Float &C, in Interpolate()
31 sw::SIMD::Float interpolant = C; in Interpolate()
137 …dst.move(i, x + ((SIMD::Float(CmpLT(x, src.Float(i)) & SIMD::Int(1)) * SIMD::Float(2.0f)) - SIMD::… in EmitExtGLSLstd450()
138 …SIMD::Float(CmpEQ(Frac(src.Float(i)), SIMD::Float(0.5f)) & SIMD::Int(1)) * SIMD::Float(Int4(x) & S… in EmitExtGLSLstd450()
208 dst.move(i, CmpNLT(x.Float(i), edge.Float(i)) & As<SIMD::Int>(SIMD::Float(1.0f))); in EmitExtGLSLstd450()
221 SIMD::Float(0.0f)), in EmitExtGLSLstd450()
222 SIMD::Float(1.0f)); in EmitExtGLSLstd450()
276 …auto neg = As<SIMD::Int>(CmpLT(src.Float(i), SIMD::Float(-0.0f))) & As<SIMD::Int>(SIMD::Float(-1.0… in EmitExtGLSLstd450()
277 …auto pos = As<SIMD::Int>(CmpNLE(src.Float(i), SIMD::Float(+0.0f))) & As<SIMD::Int>(SIMD::Float(1.0… in EmitExtGLSLstd450()
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DShaderCore.hpp86 // SIMD contains types that represent multiple scalars packed into a single
87 // vector data type. Types in the SIMD namespace provide a semantic hint
90 namespace SIMD { namespace
92 // Width is the number of per-lane scalars packed into each SIMD vector.
103 Pointer(rr::Pointer<Byte> base, rr::Int limit, SIMD::Int offset);
104 Pointer(rr::Pointer<Byte> base, unsigned int limit, SIMD::Int offset);
109 Pointer operator+(SIMD::Int i);
110 Pointer operator*(SIMD::Int i);
118 SIMD::Int offsets() const;
120 SIMD::Int isInBounds(unsigned int accessSize, OutOfBoundsBehavior robustness) const;
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DSpirvShaderGroup.cpp24 // |TYPE| should be the type of the binary operation (as a SIMD::<ScalarType>).
41 …auto mask = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations active. See … in BinaryOperation()
43 SIMD::UInt v_uint = (value.UInt(i) & mask) | (As<SIMD::UInt>(identity) & ~mask); in BinaryOperation()
81 …static_assert(SIMD::Width == 4, "EmitGroupNonUniform makes many assumptions that the SIMD vector w… in EmitGroupNonUniform()
96 …SIMD::Int active = state->activeLaneMask(); // Considers helper invocations active. See b/1511370… in EmitGroupNonUniform()
99 auto v0111 = SIMD::Int(0, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); in EmitGroupNonUniform()
108 …dst.move(0, AndAll(predicate.UInt(0) | ~As<SIMD::UInt>(state->activeLaneMask()))); // Considers h… in EmitGroupNonUniform()
115 …dst.move(0, OrAll(predicate.UInt(0) & As<SIMD::UInt>(state->activeLaneMask()))); // Considers hel… in EmitGroupNonUniform()
122 auto res = SIMD::UInt(0xffffffff); in EmitGroupNonUniform()
123 …SIMD::UInt active = As<SIMD::UInt>(state->activeLaneMask()); // Considers helper invocations acti… in EmitGroupNonUniform()
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DShaderCore.cpp561 SIMD::UInt halfToFloatBits(SIMD::UInt halfBits) in halfToFloatBits()
563 auto magic = SIMD::UInt(126 << 23); in halfToFloatBits()
565 auto sign16 = halfBits & SIMD::UInt(0x8000); in halfToFloatBits()
566 auto man16 = halfBits & SIMD::UInt(0x03FF); in halfToFloatBits()
567 auto exp16 = halfBits & SIMD::UInt(0x7C00); in halfToFloatBits()
569 auto isDnormOrZero = CmpEQ(exp16, SIMD::UInt(0)); in halfToFloatBits()
570 auto isInfOrNaN = CmpEQ(exp16, SIMD::UInt(0x7C00)); in halfToFloatBits()
574 auto exp32 = (exp16 + SIMD::UInt(0x1C000)) << 13; in halfToFloatBits()
575 auto norm32 = (man32 | exp32) | (isInfOrNaN & SIMD::UInt(0x7F800000)); in halfToFloatBits()
577 auto denorm32 = As<SIMD::UInt>(As<SIMD::Float>(magic + man16) - As<SIMD::Float>(magic)); in halfToFloatBits()
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DComputeProgram.cpp74 …:BuiltInNumWorkgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
78 As<SIMD::Float>(SIMD::Int(Extract(routine->numWorkgroups, component))); in setWorkgroupBuiltins()
82 …v::BuiltInWorkgroupId, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
86 As<SIMD::Float>(SIMD::Int(workgroupID[component])); in setWorkgroupBuiltins()
90 …:BuiltInWorkgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
94 As<SIMD::Float>(SIMD::Int(Extract(routine->workgroupSize, component))); in setWorkgroupBuiltins()
98 …::BuiltInNumSubgroups, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
100 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->subgroupsPerWorkgroup)); in setWorkgroupBuiltins()
103 …::BuiltInSubgroupSize, [&](const SpirvShader::BuiltinMapping &builtin, Array<SIMD::Float> &value) { in setWorkgroupBuiltins()
105 value[builtin.FirstComponent] = As<SIMD::Float>(SIMD::Int(routine->invocationsPerSubgroup)); in setWorkgroupBuiltins()
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DSpirvShaderArithmetic.cpp48 SIMD::Float v = lhs.Float(i) * rhs.Float(0); in EmitMatrixTimesVector()
68 SIMD::Float v = lhs.Float(0) * rhs.Float(i * lhs.componentCount); in EmitVectorTimesMatrix()
94 SIMD::Float v = SIMD::Float(0); in EmitMatrixTimesMatrix()
166 auto one = SIMD::UInt(1); in EmitUnaryOp()
177 auto one = SIMD::UInt(1); in EmitUnaryOp()
179 SIMD::UInt out = (v >> offset) & Bitmask32(count); in EmitUnaryOp()
195 SIMD::UInt v = src.UInt(i); in EmitUnaryOp()
196 v = ((v >> 1) & SIMD::UInt(0x55555555)) | ((v & SIMD::UInt(0x55555555)) << 1); in EmitUnaryOp()
197 v = ((v >> 2) & SIMD::UInt(0x33333333)) | ((v & SIMD::UInt(0x33333333)) << 2); in EmitUnaryOp()
198 v = ((v >> 4) & SIMD::UInt(0x0F0F0F0F)) | ((v & SIMD::UInt(0x0F0F0F0F)) << 4); in EmitUnaryOp()
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/third_party/skia/m133/third_party/externals/libjpeg-turbo/
DBUILD.gn34 include_dirs = [ "simd/nasm/" ]
37 "simd/nasm/jdct.inc",
38 "simd/nasm/jsimdext.inc",
42 include_dirs += [ "simd/i386/" ]
44 "simd/i386/jccolor-avx2.asm",
45 "simd/i386/jccolor-mmx.asm",
46 "simd/i386/jccolor-sse2.asm",
47 "simd/i386/jcgray-avx2.asm",
48 "simd/i386/jcgray-mmx.asm",
49 "simd/i386/jcgray-sse2.asm",
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/third_party/skia/third_party/externals/libjpeg-turbo/
DBUILD.gn31 include_dirs = [ "simd/nasm/" ]
34 include_dirs += [ "simd/i386/" ]
36 "simd/i386/jccolor-avx2.asm",
37 "simd/i386/jccolor-mmx.asm",
38 "simd/i386/jccolor-sse2.asm",
39 "simd/i386/jcgray-avx2.asm",
40 "simd/i386/jcgray-mmx.asm",
41 "simd/i386/jcgray-sse2.asm",
42 "simd/i386/jchuff-sse2.asm",
43 "simd/i386/jcphuff-sse2.asm",
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/third_party/rust/rust/library/portable-simd/crates/core_simd/src/ops/
Dderef.rs1 //! This module hacks in "implicit deref" for Simd's operators.
8 (impl<T, const LANES: usize> $trait:ident for $simd:ty {
11 impl<T, const LANES: usize> $trait<$simd> for &$simd
14 $simd: $trait<$simd, Output = $simd>,
17 type Output = Simd<T, LANES>;
21 fn $call(self, rhs: $simd) -> Self::Output {
29 (impl<T, const LANES: usize> $trait:ident for $simd:ty {
32 impl<T, const LANES: usize> $trait<&$simd> for $simd
35 $simd: $trait<$simd, Output = $simd>,
38 type Output = Simd<T, LANES>;
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Dunary.rs1 use crate::simd::intrinsics;
2 use crate::simd::{LaneCount, Simd, SimdElement, SupportedLaneCount};
6 ($(impl<const LANES: usize> Neg for Simd<$scalar:ty, LANES>)*) => {
7 $(impl<const LANES: usize> Neg for Simd<$scalar, LANES>
25 impl<const LANES: usize> Neg for Simd<f32, LANES>
27 impl<const LANES: usize> Neg for Simd<f64, LANES>
29 impl<const LANES: usize> Neg for Simd<i8, LANES>
31 impl<const LANES: usize> Neg for Simd<i16, LANES>
33 impl<const LANES: usize> Neg for Simd<i32, LANES>
35 impl<const LANES: usize> Neg for Simd<i64, LANES>
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/third_party/rust/rust/library/portable-simd/crates/core_simd/src/
Dvector.rs1 use crate::simd::{
7 /// A SIMD vector with the shape of `[T; N]` but the operations of `T`.
9 /// `Simd<T, N>` supports the operators (+, *, etc.) that `T` does in "elementwise" fashion.
12 /// However, `Simd` differs from normal iteration and normal arrays:
13 /// - `Simd<T, N>` executes `N` operations in a single step with no `break`s
14 /// - `Simd<T, N>` can have an alignment greater than `T`, for better mechanical sympathy
16 /// By always imposing these constraints on `Simd`, it is easier to compile elementwise operations
21 /// # use core::simd::{Simd};
28 /// // `Simd<T, N>` implements `From<[T; N]>`
29 /// let (v, w) = (Simd::from(a), Simd::from(b));
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/third_party/libjpeg-turbo/
Dlibjpeg-turbo-3.1.0.tar.gz
/third_party/rust/rust/library/portable-simd/crates/core_simd/src/elements/
Dint.rs2 use crate::simd::{
3 intrinsics, LaneCount, Mask, Simd, SimdCast, SimdElement, SimdPartialOrd, SupportedLaneCount,
6 /// Operations on SIMD vectors of signed integers.
8 /// Mask type used for manipulating this SIMD vector type.
11 /// Scalar type contained by this SIMD vector type.
14 /// A SIMD vector with a different element type.
17 /// Performs elementwise conversion of this vector's elements to another SIMD-valid type.
29 /// # #[cfg(feature = "as_crate")] use core_simd::simd;
30 /// # #[cfg(not(feature = "as_crate"))] use core::simd;
31 /// # use simd::{Simd, SimdInt};
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Duint.rs2 use crate::simd::{intrinsics, LaneCount, Simd, SimdCast, SimdElement, SupportedLaneCount};
4 /// Operations on SIMD vectors of unsigned integers.
6 /// Scalar type contained by this SIMD vector type.
9 /// A SIMD vector with a different element type.
12 /// Performs elementwise conversion of this vector's elements to another SIMD-valid type.
24 /// # #[cfg(feature = "as_crate")] use core_simd::simd;
25 /// # #[cfg(not(feature = "as_crate"))] use core::simd;
26 /// # use simd::{Simd, SimdUint};
28 /// let x = Simd::from_array([2, 1, 0, MAX]);
29 /// let max = Simd::splat(MAX);
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/third_party/rust/rust/tests/ui/simd/intrinsic/
Dgeneric-comparison.rs5 #[repr(simd)]
9 #[repr(simd)]
29 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
31 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
33 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
35 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
37 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
39 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
42 //~^ ERROR expected SIMD return type, found non-SIMD `i32` in main()
44 //~^ ERROR expected SIMD return type, found non-SIMD `i32` in main()
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Dgeneric-arithmetic-2.rs5 #[repr(simd)]
9 #[repr(simd)]
13 #[repr(simd)]
70 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
72 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
74 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
76 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
78 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
80 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
82 //~^ ERROR expected SIMD input type, found non-SIMD `i32` in main()
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Dgeneric-arithmetic-2.stderr1 …]: invalid monomorphization of `simd_add` intrinsic: expected SIMD input type, found non-SIMD `i32`
7 …]: invalid monomorphization of `simd_sub` intrinsic: expected SIMD input type, found non-SIMD `i32`
13 …]: invalid monomorphization of `simd_mul` intrinsic: expected SIMD input type, found non-SIMD `i32`
19 …]: invalid monomorphization of `simd_div` intrinsic: expected SIMD input type, found non-SIMD `i32`
25 …]: invalid monomorphization of `simd_shl` intrinsic: expected SIMD input type, found non-SIMD `i32`
31 …]: invalid monomorphization of `simd_shr` intrinsic: expected SIMD input type, found non-SIMD `i32`
37 …]: invalid monomorphization of `simd_and` intrinsic: expected SIMD input type, found non-SIMD `i32`
43 …1]: invalid monomorphization of `simd_or` intrinsic: expected SIMD input type, found non-SIMD `i32`
49 …]: invalid monomorphization of `simd_xor` intrinsic: expected SIMD input type, found non-SIMD `i32`
55 …]: invalid monomorphization of `simd_neg` intrinsic: expected SIMD input type, found non-SIMD `i32`
/third_party/skia/m133/bazel/external/libjpeg_turbo/
DBUILD.bazel87 "simd/arm/jccolor-neon.c",
88 "simd/arm/jcgray-neon.c",
89 "simd/arm/jchuff.h",
90 "simd/arm/jcphuff-neon.c",
91 "simd/arm/jcsample-neon.c",
92 "simd/arm/jdcolor-neon.c",
93 "simd/arm/jdmerge-neon.c",
94 "simd/arm/jdsample-neon.c",
95 "simd/arm/jfdctfst-neon.c",
96 "simd/arm/jfdctint-neon.c",
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/third_party/rust/rust/compiler/rustc_codegen_gcc/
Dfailing-ui-tests12.txt10 tests/ui/simd/array-type.rs
11 tests/ui/simd/intrinsic/float-minmax-pass.rs
12 tests/ui/simd/intrinsic/generic-arithmetic-saturating-pass.rs
13 tests/ui/simd/intrinsic/generic-as.rs
14 tests/ui/simd/intrinsic/generic-cast-pass.rs
15 tests/ui/simd/intrinsic/generic-cast-pointer-width.rs
16 tests/ui/simd/intrinsic/generic-comparison-pass.rs
17 tests/ui/simd/intrinsic/generic-elements-pass.rs
18 tests/ui/simd/intrinsic/generic-reduction-pass.rs
19 tests/ui/simd/intrinsic/generic-select-pass.rs
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/third_party/rust/rust/tests/ui/simd/
Dtype-len.rs5 #[repr(simd)]
6 struct empty; //~ ERROR SIMD vector cannot be empty
8 #[repr(simd)]
9 struct empty2([f32; 0]); //~ ERROR SIMD vector cannot be empty
11 #[repr(simd)]
14 #[repr(simd)]
15 struct i64f64(i64, f64); //~ ERROR SIMD vector should be homogeneous
19 #[repr(simd)]
20 struct FooV(Foo, Foo); //~ ERROR SIMD vector element type should be a primitive scalar (integer/flo…
22 #[repr(simd)]
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/third_party/mesa3d/src/intel/compiler/elk/
Delk_simd_selection.cpp72 elk_simd_should_compile(elk_simd_selection_state &state, unsigned simd) in elk_simd_should_compile() argument
74 assert(simd < SIMD_COUNT); in elk_simd_should_compile()
75 assert(!state.compiled[simd]); in elk_simd_should_compile()
79 const unsigned width = 8u << simd; in elk_simd_should_compile()
88 if (state.spilled[simd]) { in elk_simd_should_compile()
89 state.error[simd] = "Would spill"; in elk_simd_should_compile()
94 state.error[simd] = "Different than required dispatch width"; in elk_simd_should_compile()
105 if (simd > 0 && state.compiled[simd - 1] && in elk_simd_should_compile()
107 state.error[simd] = "Workgroup size already fits in smaller SIMD"; in elk_simd_should_compile()
112 state.error[simd] = "Would need more than max_threads to fit all invocations"; in elk_simd_should_compile()
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/third_party/mesa3d/src/intel/compiler/
Dbrw_simd_selection.cpp81 brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd) in brw_simd_should_compile() argument
83 assert(simd < SIMD_COUNT); in brw_simd_should_compile()
84 assert(!state.compiled[simd]); in brw_simd_should_compile()
88 const unsigned width = 8u << simd; in brw_simd_should_compile()
91 state.error[simd] = "Different than required dispatch width"; in brw_simd_should_compile()
102 if (state.spilled[simd]) { in brw_simd_should_compile()
103 state.error[simd] = "Would spill"; in brw_simd_should_compile()
115 if (simd > min_simd && workgroup_size <= (width / 2)) { in brw_simd_should_compile()
116 state.error[simd] = "Workgroup size already fits in smaller SIMD"; in brw_simd_should_compile()
121 state.error[simd] = "Would need more than max_threads to fit all invocations"; in brw_simd_should_compile()
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Dbrw_compile_cs.cpp171 const unsigned simd = devinfo->ver >= 30 ? 2 - i : i; in brw_compile_cs() local
173 if (!brw_simd_should_compile(simd_state, simd)) in brw_compile_cs()
176 const unsigned dispatch_width = 8u << simd; in brw_compile_cs()
191 v[simd] = std::make_unique<fs_visitor>(compiler, &params->base, in brw_compile_cs()
198 const bool allow_spilling = simd == 0 || in brw_compile_cs()
199 (!simd_state.compiled[simd - 1] && !brw_simd_should_compile(simd_state, simd - 1)) || in brw_compile_cs()
205 v[simd]->import_uniforms(v[first].get()); in brw_compile_cs()
209 if (run_cs(*v[simd], allow_spilling)) { in brw_compile_cs()
212 brw_simd_mark_compiled(simd_state, simd, v[simd]->spilled_any_registers); in brw_compile_cs()
214 if (devinfo->ver >= 30 && !v[simd]->spilled_any_registers && in brw_compile_cs()
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/third_party/rust/rust/library/portable-simd/
Dbeginners-guide.md2 # Beginner's Guide To SIMD
4 Hello and welcome to our SIMD basics guide!
6 Because SIMD is a subject that many programmers haven't worked with before, we thought that it's be…
10 **SIMD** stands for *Single Instruction, Multiple Data*. In other words, SIMD is when the CPU perfo…
14 …SIMD. If you can't make the register go any faster, you can still make the register *wider*. This …
18 SIMD has a few special vocabulary terms you should know:
20 * **Vector:** A SIMD value is called a vector. This shouldn't be confused with the `Vec<T>` type. A…
22 * **Vectorize**: An operation that uses SIMD instructions to operate over a vector is often referre…
24 …ally recognize a situation where scalar instructions may be replaced with SIMD instructions, and u…
26 …rm is mostly used to differentiate between vectorized operations that use SIMD instructions and sc…
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