| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
32 A physical connector on the motherboard that accepts a single memory
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
45 same branch can be used in single mode or in lockstep mode. When
50 of correcting more errors than on single mode.
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
87 * Supplied by chip level and returned by the chip entry function xxx_identify,
93 * initialize &komeda_dev->format_table, this function should be called
100 * for CHIP to report or add pipeline and component resources to CORE
103 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
112 * for CORE to get the HW event from the CHIP when interrupt happened.
139 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
141 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
142 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
143 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
[all …]
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| D | irq-aspeed-i2c-ic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2017 ASPEED Technology Inc.
28 * The aspeed chip provides a single hardware interrupt for all of the I2C
29 * busses, so we use a dummy interrupt chip to translate this single interrupt
30 * into multiple interrupts, each associated with a single I2C bus.
35 struct irq_chip *chip = irq_desc_get_chip(desc); in aspeed_i2c_ic_irq_handler() local
38 chained_irq_enter(chip, desc); in aspeed_i2c_ic_irq_handler()
39 status = readl(i2c_ic->base); in aspeed_i2c_ic_irq_handler()
41 generic_handle_domain_irq(i2c_ic->irq_domain, bit); in aspeed_i2c_ic_irq_handler()
43 chained_irq_exit(chip, desc); in aspeed_i2c_ic_irq_handler()
[all …]
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| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | pcf8591.rst | 17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
39 - mode 2 : single ended and differential mixed
[all …]
|
| D | ltc2978.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
[all …]
|
| D | ads7828.rst | 6 * Texas Instruments/Burr-Brown ADS7828
23 - Steve Hardy <shardy@redhat.com>
24 - Vivien Didelot <vivien.didelot@savoirfairelinux.com>
25 - Guillaume Roguez <guillaume.roguez@savoirfairelinux.com>
28 -------------
34 set to true for differential mode, false for default single ended mode.
43 bounded with limits accepted by the chip, described in the datasheet.
45 If no structure is provided, the configuration defaults to single ended
49 -----------
53 The ADS7828 device is a 12-bit 8-channel A/D converter, while the ADS7830 does
[all …]
|
| /kernel/linux/linux-6.6/Documentation/hwmon/ |
| D | pcf8591.rst | 17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
39 - mode 2 : single ended and differential mixed
[all …]
|
| D | ltc2978.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
[all …]
|
| D | ads7828.rst | 6 * Texas Instruments/Burr-Brown ADS7828
23 - Steve Hardy <shardy@redhat.com>
24 - Vivien Didelot <vivien.didelot@savoirfairelinux.com>
25 - Guillaume Roguez <guillaume.roguez@savoirfairelinux.com>
28 -------------
34 set to true for differential mode, false for default single ended mode.
43 bounded with limits accepted by the chip, described in the datasheet.
45 If no structure is provided, the configuration defaults to single ended
49 -----------
53 The ADS7828 device is a 12-bit 8-channel A/D converter, while the ADS7830 does
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/hwmon/ |
| D | ina3221.txt | 5 - compatible: Must be "ti,ina3221"
6 - reg: I2C address
9 - ti,single-shot: This chip has two power modes: single-shot (chip takes one
11 chip takes continuous measurements). The continuous mode is
13 but the single-shot mode is more power-friendly and useful
14 for battery-powered device which cares power consumptions
16 If this property is present, the single-shot mode will be
22 - #address-cells: Required only if a child node is present. Must be 1.
23 - #size-cells: Required only if a child node is present. Must be 0.
27 - reg: Must be 0, 1 or 2, corresponding to IN1, IN2 or IN3 port of INA3221
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwmon/ |
| D | ina3221.txt | 5 - compatible: Must be "ti,ina3221"
6 - reg: I2C address
9 - ti,single-shot: This chip has two power modes: single-shot (chip takes one
11 chip takes continuous measurements). The continuous mode is
13 but the single-shot mode is more power-friendly and useful
14 for battery-powered device which cares power consumptions
16 If this property is present, the single-shot mode will be
22 - #address-cells: Required only if a child node is present. Must be 1.
23 - #size-cells: Required only if a child node is present. Must be 0.
27 - reg: Must be 0, 1 or 2, corresponding to IN1, IN2 or IN3 port of INA3221
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
87 * Supplied by chip level and returned by the chip entry function xxx_identify,
93 * initialize &komeda_dev->format_table, this function should be called
100 * for CHIP to report or add pipeline and component resources to CORE
103 /** @cleanup: call to chip to cleanup komeda_dev->chip data */
112 * for CORE to get the HW event from the CHIP when interrupt happened.
139 * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
141 * - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
142 * - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
143 * - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
[all …]
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-aspeed-i2c-ic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2017 ASPEED Technology Inc.
28 * The aspeed chip provides a single hardware interrupt for all of the I2C
29 * busses, so we use a dummy interrupt chip to translate this single interrupt
30 * into multiple interrupts, each associated with a single I2C bus.
35 struct irq_chip *chip = irq_desc_get_chip(desc); in aspeed_i2c_ic_irq_handler() local
39 chained_irq_enter(chip, desc); in aspeed_i2c_ic_irq_handler()
40 status = readl(i2c_ic->base); in aspeed_i2c_ic_irq_handler()
42 bus_irq = irq_find_mapping(i2c_ic->irq_domain, bit); in aspeed_i2c_ic_irq_handler()
45 chained_irq_exit(chip, desc); in aspeed_i2c_ic_irq_handler()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/bridge/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
26 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone.
50 ChromeOS EC ANX7688 is an ultra-low power
51 4K Ultra-HD (4096x2160p60) mobile HD transmitter
53 2.0 to DisplayPort 1.3 Ultra-HD. It is connected
60 Driver for display connectors with support for DDC and hot-plug
64 on ARM-based platforms. Saying Y here when this driver is not needed
74 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
89 ITE IT6505 DisplayPort bridge chip driver.
[all …]
|
| /kernel/linux/linux-6.6/kernel/irq/ |
| D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
48 * If the underlying implementation uses a single HW irq on in irq_reserve_ipi()
49 * all cpus then we only need a single Linux irq number for in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
78 virq = irq_domain_alloc_descs(-1, nr_irqs, 0, NUMA_NO_NODE, NULL); in irq_reserve_ipi()
81 return -ENOMEM; in irq_reserve_ipi()
[all …]
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| D | generic-chip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
22 * irq_gc_noop - NOOP function
31 * irq_gc_mask_disable_reg - Mask chip via disable register
34 * Chip has separate enable/disable registers instead of a single mask
41 u32 mask = d->mask; in irq_gc_mask_disable_reg()
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
45 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_reg()
51 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
54 * Chip has a single mask register. Values of this register are cached
[all …]
|
| /kernel/linux/linux-5.10/kernel/irq/ |
| D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
48 * If the underlying implementation uses a single HW irq on in irq_reserve_ipi()
49 * all cpus then we only need a single Linux irq number for in irq_reserve_ipi()
74 return -EINVAL; in irq_reserve_ipi()
78 virq = irq_domain_alloc_descs(-1, nr_irqs, 0, NUMA_NO_NODE, NULL); in irq_reserve_ipi()
81 return -ENOMEM; in irq_reserve_ipi()
[all …]
|
| D | generic-chip.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
22 * irq_gc_noop - NOOP function
30 * irq_gc_mask_disable_reg - Mask chip via disable register
33 * Chip has separate enable/disable registers instead of a single mask
40 u32 mask = d->mask; in irq_gc_mask_disable_reg()
43 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
44 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_reg()
49 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
52 * Chip has a single mask register. Values of this register are cached
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/ti/wl12xx/ |
| D | wl12xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /* WiLink 6/7 chip IDs */
19 /* FW chip version for wl127x */
21 /* minimum single-role FW version for wl127x */
26 /* minimum multi-role FW version for wl127x */
32 /* FW chip version for wl128x */
34 /* minimum single-role FW version for wl128x */
39 /* minimum multi-role FW version for wl128x */
127 * A bitmap (where each bit represents a single HLID)
133 * A bitmap (where each bit represents a single HLID) to indicate
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/wireless/ti/wl12xx/ |
| D | wl12xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /* WiLink 6/7 chip IDs */
19 /* FW chip version for wl127x */
21 /* minimum single-role FW version for wl127x */
26 /* minimum multi-role FW version for wl127x */
32 /* FW chip version for wl128x */
34 /* minimum single-role FW version for wl128x */
39 /* minimum multi-role FW version for wl128x */
127 * A bitmap (where each bit represents a single HLID)
133 * A bitmap (where each bit represents a single HLID) to indicate
[all …]
|
| /kernel/linux/linux-5.10/Documentation/networking/device_drivers/wan/ |
| D | z8530book.rst | 13 services using this chip.
25 on the chip (each chip has two channels).
28 chip is interface to the I/O and interrupt facilities of the host
34 The DMA mode supports the chip when it is configured to use dual DMA
36 operation for a single channel. With DMA running the Z85230 tops out
38 noting here that many PC machines hang or crash when the chip is driven
41 Transmit DMA mode uses a single DMA channel. The DMA channel is used for
54 Having identified the chip you need to fill in a struct z8530_dev,
55 which describes each chip. This object must exist until you finally
58 interrupt number of the chip. (Each chip has a single interrupt source
[all …]
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | oxnas_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only
38 static uint8_t oxnas_nand_read_byte(struct nand_chip *chip) in oxnas_nand_read_byte() argument
40 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); in oxnas_nand_read_byte()
42 return readb(oxnas->io_base); in oxnas_nand_read_byte()
45 static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len) in oxnas_nand_read_buf() argument
47 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); in oxnas_nand_read_buf()
49 ioread8_rep(oxnas->io_base, buf, len); in oxnas_nand_read_buf()
52 static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf, in oxnas_nand_write_buf() argument
55 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); in oxnas_nand_write_buf()
57 iowrite8_rep(oxnas->io_base, buf, len); in oxnas_nand_write_buf()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
22 On Chip RAM ECC
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
|