| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| D | i2c-pasemi-core.c | 5 * SMBus host driver for PA Semi PWRficient
45 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() argument
47 dev_dbg(smbus->dev, "smbus write reg %x val %08x\n", reg, val); in reg_write()
48 iowrite32(val, smbus->ioaddr + reg); in reg_write()
51 static inline int reg_read(struct pasemi_smbus *smbus, int reg) in reg_read() argument
54 ret = ioread32(smbus->ioaddr + reg); in reg_read()
55 dev_dbg(smbus->dev, "smbus read reg %x val %08x\n", reg, ret); in reg_read()
59 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) argument
60 #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO) argument
62 static void pasemi_reset(struct pasemi_smbus *smbus) in pasemi_reset() argument
[all …]
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| D | i2c-amd8111.c | 3 * SMBus 2.0 driver for AMD-8111 IO-Hub.
21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
68 static int amd_ec_wait_write(struct amd_smbus *smbus) in amd_ec_wait_write() argument
72 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) in amd_ec_wait_write()
76 dev_warn(&smbus->dev->dev, in amd_ec_wait_write()
84 static int amd_ec_wait_read(struct amd_smbus *smbus) in amd_ec_wait_read() argument
88 while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout) in amd_ec_wait_read()
92 dev_warn(&smbus->dev->dev, in amd_ec_wait_read()
100 static int amd_ec_read(struct amd_smbus *smbus, unsigned char address, in amd_ec_read() argument
105 status = amd_ec_wait_write(smbus); in amd_ec_read()
[all …]
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| D | i2c-nforce2.c | 3 SMBus driver for nVidia nForce2 MCP
9 SMBus 2.0 driver for AMD-8111 IO-Hub
35 /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
51 MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
64 * nVidia nForce2 SMBus control register definitions
72 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
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| D | i2c-pasemi-platform.c | 5 * PA Semi PWRficient SMBus host driver for Apple SoCs
19 struct pasemi_smbus smbus; member
32 data->smbus.clk_div = DIV_ROUND_UP(clk_rate, 16 * frequency); in pasemi_platform_i2c_calc_clk_div()
33 if (data->smbus.clk_div < 4) in pasemi_platform_i2c_calc_clk_div()
34 return dev_err_probe(data->smbus.dev, -EINVAL, in pasemi_platform_i2c_calc_clk_div()
37 if (data->smbus.clk_div > 0xff) in pasemi_platform_i2c_calc_clk_div()
38 return dev_err_probe(data->smbus.dev, -EINVAL, in pasemi_platform_i2c_calc_clk_div()
49 struct pasemi_smbus *smbus; in pasemi_platform_i2c_probe() local
59 smbus = &data->smbus; in pasemi_platform_i2c_probe()
60 smbus->dev = dev; in pasemi_platform_i2c_probe()
[all …]
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| D | i2c-pasemi-pci.c | 5 * SMBus host driver for PA Semi PWRficient
28 struct pasemi_smbus *smbus; in pasemi_smb_pci_probe() local
36 smbus = devm_kzalloc(&dev->dev, sizeof(*smbus), GFP_KERNEL); in pasemi_smb_pci_probe()
37 if (!smbus) in pasemi_smb_pci_probe()
40 smbus->dev = &dev->dev; in pasemi_smb_pci_probe()
43 smbus->clk_div = CLK_100K_DIV; in pasemi_smb_pci_probe()
49 smbus->hw_rev = PASEMI_HW_REV_PCI; in pasemi_smb_pci_probe()
55 smbus->ioaddr = pcim_iomap(dev, 0, 0); in pasemi_smb_pci_probe()
56 if (!smbus->ioaddr) in pasemi_smb_pci_probe()
59 smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; in pasemi_smb_pci_probe()
[all …]
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| D | i2c-piix4.c | 18 SMBus interfaces.
38 /* PIIX4 SMBus address offsets */
187 "SMBus base address memory region 0x%x already in use.\n", in piix4_sb800_region_request()
197 dev_err(dev, "SMBus base address mapping failed.\n"); in piix4_sb800_region_request()
209 "SMBus base address index region 0x%x already in use.\n", in piix4_sb800_region_request()
234 * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on in piix4_sb800_use_mmio()
252 /* On some motherboards, it was reported that accessing the SMBus in piix4_setup()
256 "Accessing the SMBus on this system is unsafe!\n"); in piix4_setup()
260 /* Don't access SMBus on IBM systems which get corrupted eeproms */ in piix4_setup()
269 /* Determine the address of the SMBus areas */ in piix4_setup()
[all …]
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-pasemi.c | 5 * SMBus host driver for PA Semi PWRficient
52 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() argument
54 dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n", in reg_write()
55 smbus->base + reg, val); in reg_write()
56 outl(val, smbus->base + reg); in reg_write()
59 static inline int reg_read(struct pasemi_smbus *smbus, int reg) in reg_read() argument
62 ret = inl(smbus->base + reg); in reg_read()
63 dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n", in reg_read()
64 smbus->base + reg, ret); in reg_read()
68 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) argument
[all …]
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| D | i2c-amd8111.c | 3 * SMBus 2.0 driver for AMD-8111 IO-Hub.
21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
68 static int amd_ec_wait_write(struct amd_smbus *smbus) in amd_ec_wait_write() argument
72 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) in amd_ec_wait_write()
76 dev_warn(&smbus->dev->dev, in amd_ec_wait_write()
84 static int amd_ec_wait_read(struct amd_smbus *smbus) in amd_ec_wait_read() argument
88 while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout) in amd_ec_wait_read()
92 dev_warn(&smbus->dev->dev, in amd_ec_wait_read()
100 static int amd_ec_read(struct amd_smbus *smbus, unsigned char address, in amd_ec_read() argument
105 status = amd_ec_wait_write(smbus); in amd_ec_read()
[all …]
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| D | i2c-nforce2.c | 3 SMBus driver for nVidia nForce2 MCP
9 SMBus 2.0 driver for AMD-8111 IO-Hub
35 /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
51 MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
64 * nVidia nForce2 SMBus control register definitions
72 * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
[all …]
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| D | i2c-piix4.c | 18 SMBus interfaces.
38 /* PIIX4 SMBus address offsets */
177 /* On some motherboards, it was reported that accessing the SMBus in piix4_setup()
181 "Accessing the SMBus on this system is unsafe!\n"); in piix4_setup()
185 /* Don't access SMBus on IBM systems which get corrupted eeproms */ in piix4_setup()
194 /* Determine the address of the SMBus areas */ in piix4_setup()
202 dev_err(&PIIX4_dev->dev, "SMBus base address " in piix4_setup()
213 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", in piix4_setup()
226 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " in piix4_setup()
231 * noted that many Dell machines have the SMBus in piix4_setup()
[all …]
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| /kernel/linux/linux-6.6/Documentation/i2c/ |
| D | functionality.rst | 2 I2C/SMBus Functionality
8 Because not every I2C or SMBus adapter implements everything in the
22 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus
29 I2C_FUNC_SMBUS_QUICK Handles the SMBus write_quick command
30 I2C_FUNC_SMBUS_READ_BYTE Handles the SMBus read_byte command
31 I2C_FUNC_SMBUS_WRITE_BYTE Handles the SMBus write_byte command
32 I2C_FUNC_SMBUS_READ_BYTE_DATA Handles the SMBus read_byte_data command
33 I2C_FUNC_SMBUS_WRITE_BYTE_DATA Handles the SMBus write_byte_data command
34 I2C_FUNC_SMBUS_READ_WORD_DATA Handles the SMBus read_word_data command
35 I2C_FUNC_SMBUS_WRITE_WORD_DATA Handles the SMBus write_byte_data command
[all …]
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| D | smbus-protocol.rst | 2 The SMBus Protocol
5 The following is a summary of the SMBus protocol. It applies to
10 Some adapters understand only the SMBus (System Management Bus) protocol,
12 only the same subset, which makes it possible to put them on an SMBus.
14 If you write a driver for some I2C device, please try to use the SMBus
17 SMBus adapters and I2C adapters (the SMBus command set is automatically
19 handled at all on most pure SMBus adapters).
21 Below is a list of SMBus protocol operations, and the functions executing
22 them. Note that the names used in the SMBus protocol specifications usually
24 single data byte, the functions using SMBus protocol operation names execute
[all …]
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| D | fault-codes.rst | 2 I2C/SMBUS Fault Codes
6 codes in the I2C/SMBus stack.
26 I2C and SMBus fault codes
52 Returned by SMBus logic when an invalid Packet Error Code byte
55 fault is only reported on read transactions; the SMBus slave
61 Returned by SMBus adapters when the bus was busy for longer
63 SMBus adapter) needs some fault recovery (such as resetting),
102 doesn't support SMBus block transfers is asked to execute
115 or SMBus (or chip-specific) protocol specifications. One
116 case is when the length of an SMBus block data response
[all …]
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| /kernel/linux/linux-5.10/Documentation/i2c/ |
| D | functionality.rst | 2 I2C/SMBus Functionality
8 Because not every I2C or SMBus adapter implements everything in the
22 I2C_FUNC_I2C Plain i2c-level commands (Pure SMBus
29 I2C_FUNC_SMBUS_QUICK Handles the SMBus write_quick command
30 I2C_FUNC_SMBUS_READ_BYTE Handles the SMBus read_byte command
31 I2C_FUNC_SMBUS_WRITE_BYTE Handles the SMBus write_byte command
32 I2C_FUNC_SMBUS_READ_BYTE_DATA Handles the SMBus read_byte_data command
33 I2C_FUNC_SMBUS_WRITE_BYTE_DATA Handles the SMBus write_byte_data command
34 I2C_FUNC_SMBUS_READ_WORD_DATA Handles the SMBus read_word_data command
35 I2C_FUNC_SMBUS_WRITE_WORD_DATA Handles the SMBus write_byte_data command
[all …]
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| D | smbus-protocol.rst | 2 The SMBus Protocol
5 The following is a summary of the SMBus protocol. It applies to
10 Some adapters understand only the SMBus (System Management Bus) protocol,
12 only the same subset, which makes it possible to put them on an SMBus.
14 If you write a driver for some I2C device, please try to use the SMBus
17 SMBus adapters and I2C adapters (the SMBus command set is automatically
19 handled at all on most pure SMBus adapters).
21 Below is a list of SMBus protocol operations, and the functions executing
22 them. Note that the names used in the SMBus protocol specifications usually
24 single data byte, the functions using SMBus protocol operation names execute
[all …]
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| D | fault-codes.rst | 2 I2C/SMBUS Fault Codes
6 codes in the I2C/SMBus stack.
26 I2C and SMBus fault codes
52 Returned by SMBus logic when an invalid Packet Error Code byte
55 fault is only reported on read transactions; the SMBus slave
61 Returned by SMBus adapters when the bus was busy for longer
63 SMBus adapter) needs some fault recovery (such as resetting),
102 doesn't support SMBus block transfers is asked to execute
115 or SMBus (or chip-specific) protocol specifications. One
116 case is when the length of an SMBus block data response
[all …]
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| /kernel/linux/linux-5.10/Documentation/i2c/busses/ |
| D | i2c-i801.rst | 51 On Intel Patsburg and later chipsets, both the normal host SMBus controller
69 0x01 disable SMBus PEC
73 0x20 disable SMBus Host Notify
95 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial
99 SMBus controller.
114 SMBus 2.0 Support
117 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
126 Hidden ICH SMBus
130 SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the
136 SMBus was hidden on purpose because it'll be driven by ACPI. If the
[all …]
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| D | i2c-piix4.rst | 45 SMBus - you can not access it on I2C levels. The good news is that it
46 natively understands SMBus commands and you do not have to worry about
47 timing problems. The bad news is that non-SMBus devices connected to it can
58 find such an entry, you have a PIIX4 SMBus controller.
60 On some computers (most notably, some Dells), the SMBus is disabled by
67 'force' foes, but it will also set a new base I/O port address. The SMBus
74 The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use
78 identical to the PIIX4 in I2C/SMBus support.
81 PIIX4-compatible SMBus controllers. If your BIOS initializes the
83 an "Auxiliary SMBus Host Controller".
[all …]
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| D | i2c-amd8111.rst | 6 * AMD-8111 SMBus 2.0 PCI interface
20 00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
21 Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
32 SMBus 2.0 Support
41 Note that for the 8111, there are two SMBus adapters. The SMBus 2.0 adapter
42 is supported by this driver, and the SMBus 1.0 adapter is supported by the
|
| /kernel/linux/linux-6.6/Documentation/i2c/busses/ |
| D | i2c-i801.rst | 56 On Intel Patsburg and later chipsets, both the normal host SMBus controller
74 0x01 disable SMBus PEC
78 0x20 disable SMBus Host Notify
100 The SMBus controller is function 3 in device 1f. Class 0c05 is SMBus Serial
104 SMBus controller.
119 SMBus 2.0 Support
122 The 82801DB (ICH4) and later chips support several SMBus 2.0 features.
131 Hidden ICH SMBus
135 SMBus device at 00:1f.3 in lspci, and you can't figure out any way in the
141 SMBus was hidden on purpose because it'll be driven by ACPI. If the
[all …]
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| D | i2c-piix4.rst | 45 SMBus - you can not access it on I2C levels. The good news is that it
46 natively understands SMBus commands and you do not have to worry about
47 timing problems. The bad news is that non-SMBus devices connected to it can
58 find such an entry, you have a PIIX4 SMBus controller.
60 On some computers (most notably, some Dells), the SMBus is disabled by
67 'force' does, but it will also set a new base I/O port address. The SMBus
74 The PIIX/PIIX3 does not implement an SMBus or I2C bus, so you can't use
78 identical to the PIIX4 in I2C/SMBus support.
81 PIIX4-compatible SMBus controllers. If your BIOS initializes the
83 an "Auxiliary SMBus Host Controller".
[all …]
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| D | i2c-amd8111.rst | 6 * AMD-8111 SMBus 2.0 PCI interface
20 00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
21 Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
32 SMBus 2.0 Support
41 Note that for the 8111, there are two SMBus adapters. The SMBus 2.0 adapter
42 is supported by this driver, and the SMBus 1.0 adapter is supported by the
|
| /kernel/linux/linux-6.6/drivers/i2c/ |
| D | i2c-core-smbus.c | 3 * Linux I2C core SMBus and SMBus emulation code
5 * This file contains the SMBus functions which are always included in the I2C
6 * core because they can be emulated via I2C. SMBus specific extensions
7 * (e.g. smbalert) are handled in a separate i2c-smbus module.
9 * All SMBus-related things are written by Frodo Looijaard <frodol@dds.nl>
10 * SMBus 2.0 support by Mark Studebaker <mdsxyz123@yahoo.com> and
16 #include <linux/i2c-smbus.h>
23 #include <trace/events/smbus.h>
26 /* The SMBus parts */
59 /* Assume a 7-bit address, which is reasonable for SMBus */
[all …]
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| /kernel/linux/linux-5.10/drivers/i2c/ |
| D | i2c-core-smbus.c | 3 * Linux I2C core SMBus and SMBus emulation code
5 * This file contains the SMBus functions which are always included in the I2C
6 * core because they can be emulated via I2C. SMBus specific extensions
7 * (e.g. smbalert) are handled in a separate i2c-smbus module.
9 * All SMBus-related things are written by Frodo Looijaard <frodol@dds.nl>
10 * SMBus 2.0 support by Mark Studebaker <mdsxyz123@yahoo.com> and
16 #include <linux/i2c-smbus.h>
22 #include <trace/events/smbus.h>
25 /* The SMBus parts */
50 /* Assume a 7-bit address, which is reasonable for SMBus */
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | i2c.rst | 1 I\ :sup:`2`\ C and SMBus Subsystem
29 The System Management Bus (SMBus) is a sibling protocol. Most SMBus
31 for SMBus, and it standardizes particular protocol messages and idioms.
32 Controllers that support I2C can also support most SMBus operations, but
33 SMBus controllers don't support all the protocol options that an I2C
34 controller will. There are functions to perform various SMBus protocol
35 operations, either using I2C primitives or by issuing SMBus commands to
47 .. kernel-doc:: drivers/i2c/i2c-core-smbus.c
|