| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
[all …]
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| D | socionext,uniphier-soc-glue-debug.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
[all …]
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| D | socionext,uniphier-ahci-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC AHCI glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
19 - enum:
20 - socionext,uniphier-pro4-ahci-glue
21 - socionext,uniphier-pxs2-ahci-glue
[all …]
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| D | socionext,uniphier-dwc3-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
67 This selects the Anarion SoC glue layer support for the stmmac driver.
77 This selects Ingenic SoCs glue layer support for the stmmac
89 This selects the IPQ806x SoC glue layer support for the stmmac
91 acceleration features available on this SoC. Network devices
92 will behave like standard non-accelerated ethernet interfaces.
95 fixup based on the ipq806x SoC revision.
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
45 tristate "Support for snps,dwc-qos-ethernet.txt DT binding."
50 Support for chips using the snps,dwc-qos-ethernet.txt DT binding.
67 This selects the Anarion SoC glue layer support for the stmmac driver.
77 This selects the IPQ806x SoC glue layer support for the stmmac
79 acceleration features available on this SoC. Network devices
80 will behave like standard non-accelerated ethernet interfaces.
96 This selects the MT2712 SoC support for the stmmac driver.
105 This selects the Amlogic Meson SoC glue layer support for
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | uniphier-reset.txt | 1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
5 -----------------------------------
7 Some peripheral core reset belongs to its own glue layer. Before using
12 - compatible: Should be
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | uniphier-regulator.txt | 7 ---------------
9 This regulator controls VBUS and belongs to USB3 glue layer. Before using
14 - compatible: Should be
15 "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
16 "socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC
17 "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
18 "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
19 "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
20 - reg: Specifies offset and length of the register set for the device.
21 - clocks: A list of phandles to the clock gate for USB3 glue layer.
[all …]
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| /kernel/linux/linux-5.10/sound/soc/meson/ |
| D | Makefile | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 snd-soc-meson-aiu-objs := aiu.o
4 snd-soc-meson-aiu-objs += aiu-acodec-ctrl.o
5 snd-soc-meson-aiu-objs += aiu-codec-ctrl.o
6 snd-soc-meson-aiu-objs += aiu-encoder-i2s.o
7 snd-soc-meson-aiu-objs += aiu-encoder-spdif.o
8 snd-soc-meson-aiu-objs += aiu-fifo.o
9 snd-soc-meson-aiu-objs += aiu-fifo-i2s.o
10 snd-soc-meson-aiu-objs += aiu-fifo-spdif.o
11 snd-soc-meson-axg-fifo-objs := axg-fifo.o
[all …]
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| /kernel/linux/linux-6.6/sound/soc/meson/ |
| D | Makefile | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 snd-soc-meson-aiu-objs := aiu.o
4 snd-soc-meson-aiu-objs += aiu-acodec-ctrl.o
5 snd-soc-meson-aiu-objs += aiu-codec-ctrl.o
6 snd-soc-meson-aiu-objs += aiu-encoder-i2s.o
7 snd-soc-meson-aiu-objs += aiu-encoder-spdif.o
8 snd-soc-meson-aiu-objs += aiu-fifo.o
9 snd-soc-meson-aiu-objs += aiu-fifo-i2s.o
10 snd-soc-meson-aiu-objs += aiu-fifo-spdif.o
11 snd-soc-meson-axg-fifo-objs := axg-fifo.o
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/nvmem/ |
| D | uniphier-efuse.txt | 3 This UniPhier eFuse must be under soc-glue.
6 - compatible: should be "socionext,uniphier-efuse"
7 - reg: should contain the register location and length
15 soc-glue@5f900000 {
16 compatible = "socionext,uniphier-ld20-soc-glue-debug",
17 "simple-mfd";
18 #address-cells = <1>;
19 #size-cells = <1>;
23 compatible = "socionext,uniphier-efuse";
28 compatible = "socionext,uniphier-efuse";
[all …]
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| /kernel/linux/linux-6.6/drivers/usb/musb/ |
| D | mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
58 spin_lock_irqsave(&musb->lock, flags); in mpfs_musb_interrupt()
60 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); in mpfs_musb_interrupt()
61 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); in mpfs_musb_interrupt()
62 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); in mpfs_musb_interrupt()
64 if (musb->int_usb || musb->int_tx || musb->int_rx) { in mpfs_musb_interrupt()
65 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); in mpfs_musb_interrupt()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | mediatek,mtk-xhci.txt | 3 The device node for Mediatek SOC USB3.0 host controller
6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
[all …]
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| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
[all …]
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| D | mediatek,mtu3.txt | 4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
6 when using "mediatek,mtu3" compatible string, you need SoC specific
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | sti-dwmac.txt | 1 STMicroelectronics SoC DWMAC glue layer controller
5 and what is needed on STi platforms to program the stmmac glue logic.
10 - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac",
11 "st,stih407-dwmac", "st,stid127-dwmac".
12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 encompases the glue register, and the offset of the control register.
14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 register available on STiH407 SoC.
16 - pinctrl-0: pin-control for all the MII mode supported.
19 - resets : phandle pointing to the system reset controller with correct
[all …]
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| D | mdio-mux-meson-g12a.txt | 1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
8 - compatible : amlogic,g12a-mdio-mux
9 - reg: physical address and length of the multiplexer/glue registers
10 - clocks: list of clock phandle, one for each entry clock-names.
11 - clock-names: should contain the following:
14 * "clkin1" : SoC 50MHz MPLL
18 mdio_mux: mdio-multiplexer@4c000 {
19 compatible = "amlogic,g12a-mdio-mux";
24 clock-names = "pclk", "clkin0", "clkin1";
25 mdio-parent-bus = <&mdio0>;
[all …]
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| D | mediatek-dwmac.txt | 1 MediaTek DWMAC glue layer controller
3 This file documents platform glue layer for stmmac.
9 - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg: Address and length of the register set for the device
11 - interrupts: Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
17 "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
18 - mac-address: See ethernet.txt in the same directory
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | sti-dwmac.txt | 1 STMicroelectronics SoC DWMAC glue layer controller
5 and what is needed on STi platforms to program the stmmac glue logic.
10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
12 encompases the glue register, and the offset of the control register.
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
14 register available on STiH407 SoC.
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
12 encompasses the glue registers
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | socionext,uniphier-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
18 - socionext,uniphier-ld4-pinctrl
19 - socionext,uniphier-pro4-pinctrl
20 - socionext,uniphier-sld8-pinctrl
21 - socionext,uniphier-pro5-pinctrl
22 - socionext,uniphier-pxs2-pinctrl
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | socionext,uniphier-usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
22 - socionext,uniphier-pro4-usb2-phy
23 - socionext,uniphier-ld11-usb2-phy
[all …]
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| /kernel/linux/linux-6.6/drivers/reset/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
30 AR71xx SoC reset controller.
96 bool "Reset controller driver for Canaan Kendryte K210 SoC"
101 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
123 This driver supports switch core reset for the Microchip Sparx5 SoC.
151 This enables the reset controller driver for Nuvoton MA35D1 SoC.
160 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
165 This driver supports peripheral reset for the Microchip PolarFire SoC
190 Raspberry Pi 4's co-processor controls some of the board's HW
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/usb/ |
| D | writing_musb_glue_layer.rst | 2 Writing a MUSB Glue Layer
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
22 Ingenic JZ4740 SoC, modelled after the many MUSB glue layers in the
25 basics of the ``jz4740.c`` glue layer, explaining the different pieces and
26 what needs to be done in order to write your own device glue layer.
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
46 ------------------------
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/usb/ |
| D | writing_musb_glue_layer.rst | 2 Writing a MUSB Glue Layer
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
22 Ingenic JZ4740 SoC, modelled after the many MUSB glue layers in the
25 basics of the ``jz4740.c`` glue layer, explaining the different pieces and
26 what needs to be done in order to write your own device glue layer.
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
46 ------------------------
[all …]
|