| /kernel/linux/linux-6.6/drivers/pinctrl/qcom/ |
| D | pinctrl-sc7280-lpass-lpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * ALSA SoC platform-machine driver for QTi LPASS
11 #include "pinctrl-lpass-lpi.h"
66 PINCTRL_PIN(10, "gpio10"),
81 static const char * const i2s2_clk_groups[] = { "gpio10" };
91 static const char * const wsa_swr_clk_groups[] = { "gpio10" };
148 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
157 .name = "qcom-sc7280-lpass-lpi-pinctrl",
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | brcm,bcm6318-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6318 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
[all …]
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| D | brcm,bcm6362-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6362 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
[all …]
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| D | brcm,bcm6368-gpio-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM6368 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
20 "#size-cells": true
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | qcom-ipq4019-ap.dk07.1-c1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019-ap.dk07.1.dtsi"
7 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
8 compatible = "qcom,ipq4019-ap-dk07.1-c1";
10 soc {
13 perst-gpio = <&tlmm 38 0x1>;
21 serial_1_pins: serial1-pinmux {
23 "gpio10", "gpio11";
25 bias-disable;
28 spi_0_pins: spi-0-pinmux {
[all …]
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| D | bcm2837-rpi-cm3-io3.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "bcm2837-rpi-cm3.dtsi"
4 #include "bcm283x-rpi-usb-host.dtsi"
7 compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
16 * "NC" = not connected (no rail from the SoC)
20 gpio-line-names = "GPIO0",
30 "GPIO10",
76 pinctrl-0 = <&gpioout &alt0>;
80 hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
[all …]
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| D | bcm2835-rpi-cm1-io1.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "bcm2835-rpi-cm1.dtsi"
4 #include "bcm283x-rpi-usb-host.dtsi"
7 compatible = "raspberrypi,compute-module", "brcm,bcm2835";
16 * "NC" = not connected (no rail from the SoC)
20 gpio-line-names = "GPIO0",
30 "GPIO10",
77 pinctrl-0 = <&gpioout &alt0>;
81 hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
[all …]
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| D | qcom-ipq4019-ap.dk04.1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
25 soc {
27 serial_0_pins: serial0-pinmux {
30 bias-disable;
33 serial_1_pins: serial1-pinmux {
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | k3-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
28 /* SoC portion */
30 compatible = "hisilicon,hi4511-dw-mshc";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | k3-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
28 /* SoC portion */
30 compatible = "hisilicon,hi4511-dw-mshc";
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/ |
| D | qcom-ipq4019-ap.dk07.1-c1.dts | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include "qcom-ipq4019-ap.dk07.1.dtsi"
8 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
9 compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";
11 soc {
14 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
22 serial_1_pins: serial1-pinmux {
24 "gpio10", "gpio11";
26 bias-disable;
[all …]
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| D | qcom-ipq4019-ap.dk04.1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
25 soc {
27 serial_0_pins: serial0-pinmux {
30 bias-disable;
33 serial_1_pins: serial1-pinmux {
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | rt5659.txt | 7 - compatible : One of "realtek,rt5659" or "realtek,rt5658".
9 - reg : The I2C address of the device.
11 - interrupts : The CODEC's interrupt output.
15 - clocks: The phandle of the master clock to the CODEC
16 - clock-names: Should be "mclk"
18 - realtek,in1-differential
19 - realtek,in3-differential
20 - realtek,in4-differential
21 Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
23 - realtek,dmic1-data-pin
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,sm8250-lpass-lpi-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
25 - description: LPASS Core voting clock
26 - description: LPASS Audio voting clock
[all …]
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| D | qcom,mdm9615-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
26 interrupt-controller: true
27 '#interrupt-cells': true
[all …]
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| D | qcom,sm8450-lpass-lpi-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
[all …]
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| D | bitmain,bm1880-pinctrl.txt | 3 This binding describes the pin controller found in the BM1880 SoC.
7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-pxa/ |
| D | pxa320.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa320.c
9 * 2007-08-21: eric miao <eric.miao@marvell.com>
17 #include <linux/soc/pxa/cpu.h>
28 MFP_ADDR(GPIO10, 0x0458),
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | ipq9574-rdp418.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15 compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&spi_0_pins>;
28 pinctrl-names = "default";
32 compatible = "micron,n25q128a11", "jedec,spi-nor";
[all …]
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| D | ipq9574-rdp433.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 /dts-v1/;
14 model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
15 compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
22 stdout-path = "serial0:115200n8";
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | bitmain,bm1880-pinctrl.txt | 3 This binding describes the pin controller found in the BM1880 SoC.
7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
|
| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-lantiq.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/drivers/pinctrl/pinctrl-lantiq.h
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
102 /* soc specific callback used to apply muxing */
117 GPIO10, /* 10 */ enumerator
|
| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-lantiq.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/drivers/pinctrl/pinctrl-lantiq.h
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
101 /* soc specific callback used to apply muxing */
116 GPIO10, /* 10 */ enumerator
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm2711.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
|