| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | mpc5121_nfc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
34 /* Addresses for NFC SPARE BUFFER areas */
110 void __iomem *regs; member
127 return in_be16(prv->regs + reg); in nfc_read()
136 out_be16(prv->regs + reg, val); in nfc_write()
207 wake_up(&prv->irq_waitq); in mpc5121_nfc_irq()
221 rv = wait_event_timeout(prv->irq_waitq, in mpc5121_nfc_done()
225 dev_warn(prv->dev, in mpc5121_nfc_done()
236 u32 pagemask = chip->pagemask; in mpc5121_nfc_addr_cycle()
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| D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
90 #define MTK_NAME "mtk-nand"
151 void __iomem *regs; member
162 * supported spare size of each IP.
163 * order should be the same with the spare size bitfiled defination of
186 return (u8 *)p + i * chip->ecc.size; in data_ptr()
198 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
199 poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; in oob_ptr()
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
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| D | qcom_nandc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
192 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
195 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
199 ((chip)->reg_read_dma + \
200 ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
227 * @bam_ce - the array of BAM command elements
228 * @cmd_sgl - sgl for NAND BAM command pipe
229 * @data_sgl - sgl for NAND BAM consumer/producer pipe
230 * @bam_ce_pos - the index in bam_ce which is available for next sgl
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| D | mxc_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
24 #include <linux/platform_data/mtd-mxc_nand.h>
29 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
30 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
31 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
32 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
33 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
34 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
35 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
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| /kernel/linux/linux-6.6/drivers/mtd/nand/raw/ |
| D | mpc5121_nfc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
34 /* Addresses for NFC SPARE BUFFER areas */
110 void __iomem *regs; member
127 return in_be16(prv->regs + reg); in nfc_read()
136 out_be16(prv->regs + reg, val); in nfc_write()
207 wake_up(&prv->irq_waitq); in mpc5121_nfc_irq()
221 rv = wait_event_timeout(prv->irq_waitq, in mpc5121_nfc_done()
225 dev_warn(prv->dev, in mpc5121_nfc_done()
236 u32 pagemask = chip->pagemask; in mpc5121_nfc_addr_cycle()
[all …]
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| D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
150 void __iomem *regs; member
161 * supported spare size of each IP.
162 * order should be the same with the spare size bitfiled defination of
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
[all …]
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| D | marvell_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
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| D | qcom_nandc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
207 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
210 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
214 ((chip)->reg_read_dma + \
215 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
244 * @bam_ce - the array of BAM command elements
245 * @cmd_sgl - sgl for NAND BAM command pipe
246 * @data_sgl - sgl for NAND BAM consumer/producer pipe
247 * @last_data_desc - last DMA desc in data channel (tx/rx).
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| D | mxc_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
27 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
28 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
29 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
30 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
31 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
32 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
33 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
34 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,sc7180-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <quic_sibis@quicinc.com>
19 - qcom,sc7180-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
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| /kernel/linux/linux-6.6/drivers/mtd/nand/ |
| D | ecc-mxic.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
57 /* Spare Data Size */
74 /* SDMA Address of Spare Data */
80 /* Status bytes between each chunk of spare data */
89 void __iomem *regs; member
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic()
128 if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL) in nand_to_mxic()
140 if (section < 0 || section >= ctx->steps) in mxic_ecc_ooblayout_ecc()
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| /kernel/linux/linux-6.6/drivers/soc/tegra/fuse/ |
| D | fuse-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
52 { .compatible = "nvidia,tegra20-car", },
53 { .compatible = "nvidia,tegra30-car", },
54 { .compatible = "nvidia,tegra114-car", },
55 { .compatible = "nvidia,tegra124-car", },
56 { .compatible = "nvidia,tegra132-car", },
57 { .compatible = "nvidia,tegra210-car", },
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| /kernel/linux/linux-5.10/drivers/soc/tegra/fuse/ |
| D | fuse-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
37 { .compatible = "nvidia,tegra20-car", },
38 { .compatible = "nvidia,tegra30-car", },
39 { .compatible = "nvidia,tegra114-car", },
40 { .compatible = "nvidia,tegra124-car", },
41 { .compatible = "nvidia,tegra132-car", },
42 { .compatible = "nvidia,tegra210-car", },
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/include/asm/ |
| D | kgdb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
33 * General purpose regs:
34 * r0-r30: 64 bit
38 * FPU regs:
39 * f0-f31: 128 bit
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
49 * Unfortunately "is a 32-bit register" has a very special meaning for
53 * little for people who don't spend their spare time reading ARM architecture
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | kgdb.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
33 * General purpose regs:
34 * r0-r30: 64 bit
38 * FPU regs:
39 * f0-f31: 128 bit
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
49 * Unfortunately "is a 32-bit register" has a very special meaning for
53 * little for people who don't spend their spare time reading ARM architecture
[all …]
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| /kernel/linux/linux-6.6/drivers/thermal/tegra/ |
| D | tegra30-tsensor.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2021 GRATE-DRIVER project
74 void __iomem *regs; member
81 void __iomem *regs; member
95 err = reset_control_assert(ts->rst); in tegra_tsensor_hw_enable()
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
101 err = clk_prepare_enable(ts->clk); in tegra_tsensor_hw_enable()
103 dev_err(ts->dev, "failed to enable clock: %d\n", err); in tegra_tsensor_hw_enable()
109 err = reset_control_deassert(ts->rst); in tegra_tsensor_hw_enable()
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | dvma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-m68k/dma.h
16 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
43 #define DVMA_SIZE (DVMA_END-DVMA_START)
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
50 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
51 ~(DVMA_REGION_SIZE-1))
53 /* virt <-> phys conversions */
73 #define DVMA_SIZE (DVMA_END-DVMA_START)
76 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | dvma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-m68k/dma.h
16 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
43 #define DVMA_SIZE (DVMA_END-DVMA_START)
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
50 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
51 ~(DVMA_REGION_SIZE-1))
53 /* virt <-> phys conversions */
73 #define DVMA_SIZE (DVMA_END-DVMA_START)
76 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | mach-jive.c | 1 // SPDX-License-Identifier: GPL-2.0
31 #include <linux/platform_data/mtd-nand-s3c2410.h>
32 #include <linux/platform_data/i2c-s3c2410.h>
34 #include "hardware-s3c24xx.h"
35 #include "regs-gpio.h"
36 #include <linux/platform_data/fb-s3c2410.h>
37 #include "gpio-samsung.h"
39 #include <asm/mach-types.h>
46 #include "gpio-cfg.h"
50 #include <linux/platform_data/usb-s3c2410_udc.h>
[all …]
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | i5400_edac.c | 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
[all …]
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| D | i7300_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
106 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
170 * MTRx - Memory Technology Registers
192 [22] = "Non-Redundant Fast Reset Timeout",
195 [0] = "Memory Write error on non-redundant retry or "
203 [24] = "DIMM-Spare Copy Completed",
[all …]
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| /kernel/linux/linux-6.6/drivers/edac/ |
| D | i5400_edac.c | 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | qcom,q6v5.txt | 6 - compatible:
10 "qcom,q6v5-pil",
11 "qcom,ipq8074-wcss-pil"
12 "qcom,msm8916-mss-pil",
13 "qcom,msm8974-mss-pil"
14 "qcom,msm8996-mss-pil"
15 "qcom,msm8998-mss-pil"
16 "qcom,sc7180-mss-pil"
17 "qcom,sdm845-mss-pil"
19 - reg:
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/net/ |
| D | bpf_jit_asm.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <asm/asm-compat.h>
19 * r7-r10 scratch
20 * r14 skb->data
22 * r16-31 M[]
29 * load a spare GPR with the address of slow_path_generic and pass size
90 rlwinm r_X, r_X, 2, 32-4-2, 31-2
94 * We'll need to back up our volatile regs first; we have
96 * Allocate a new stack frame here to remain ABI-compliant in
107 PPC_STLU r1, -BPF_PPC_SLOWPATH_FRAME(r1); \
[all …]
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