| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-mt65xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | spi-ar934x.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
7 // Based on spi-mt7621.c:
9 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
10 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
12 #include <linux/clk.h>
19 #include <linux/spi/spi.h>
21 #define DRIVER_NAME "spi-ar934x"
47 struct clk *clk; member
53 int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1; in ar934x_spi_clk_div()
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| D | spi-ath79.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This driver has been based on the spi-gpio.c:
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi-mem.h>
19 #include <linux/spi/spi_bitbang.h>
21 #include <linux/clk.h>
24 #define DRV_NAME "ath79-spi"
30 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
10 #include <linux/clk.h>
15 #include <linux/spi/spi.h>
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
93 struct clk *clk; /* bus clock */ member
96 struct completion done; /* wake-up from interrupt */
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value) in sifive_spi_write() argument
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
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| D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
12 #include <linux/clk.h>
21 #include <linux/spi/spi.h>
105 struct clk *clk; member
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
117 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
119 return readl(spi->regs + reg); in mchp_corespi_read()
122 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
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| D | spi-bcmbca-hsspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCMBCA High Speed SPI Controller driver
5 * Copyright 2000-2010 Broadcom Corporation
6 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright 2019-2022 Broadcom Ltd
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
99 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
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| D | spi-meson-spifc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // Driver for Amlogic Meson SPI flash controller (SPIFC)
8 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
56 #define USER_UC_MASK ((BIT(5) - 1) << 27)
70 * @master: the SPI master
72 * @clk: input clock of the built-in baud rate generator
78 struct clk *clk; member
90 * meson_spifc_wait_ready() - wait for the current operation to terminate
91 * @spifc: the Meson SPI device
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| D | spi-loongson-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
5 #include <linux/clk.h>
14 #include <linux/spi/spi.h>
16 #include "spi-loongson.h"
18 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
21 writeb(data, spi->base + reg); in loongson_spi_write_reg()
24 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
26 return readb(spi->base + reg); in loongson_spi_read_reg()
29 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
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| D | spi-orion.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
6 * Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/spi/spi.h>
19 #include <linux/clk.h>
73 * have both is for managing the armada-370-spi case with old
95 struct clk *clk; member
96 struct clk *axi_clk;
110 return orion_spi->base + reg; in spi_reg()
135 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-ar934x.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
7 // Based on spi-mt7621.c:
9 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
10 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
12 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
20 #define DRIVER_NAME "spi-ar934x"
46 struct clk *clk; member
52 int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1; in ar934x_spi_clk_div()
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| D | spi-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
13 #include <linux/clk.h>
19 #include <linux/spi/spi.h>
21 #define DRIVER_NAME "spi-mt7621"
58 struct clk *clk; member
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| D | spi-ath79.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This driver has been based on the spi-gpio.c:
17 #include <linux/spi/spi.h>
18 #include <linux/spi/spi_bitbang.h>
20 #include <linux/clk.h>
22 #include <linux/platform_data/spi-ath79.h>
24 #define DRV_NAME "ath79-spi"
30 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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| D | spi-mpc512x-psc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC512x PSC in SPI mode driver.
7 * Hongjun Chen <hong-jun.chen@freescale.com>
23 #include <linux/clk.h>
24 #include <linux/spi/spi.h>
40 switch (mps->type) { \
42 struct mpc52xx_psc __iomem *psc = mps->psc; \
43 __ret = &psc->regname; \
47 struct mpc5125_psc __iomem *psc = mps->psc; \
48 __ret = &psc->regname; \
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| D | spi-bcm63xx-hsspi.c | 2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
13 #include <linux/clk.h>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
98 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
105 struct clk *clk; member
106 struct clk *pll_clk;
119 mutex_lock(&bs->bus_mutex); in bcm63xx_hsspi_set_cs()
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| D | spi-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
10 #include <linux/clk.h>
15 #include <linux/spi/spi.h>
38 #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39 #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
93 struct clk *clk; /* bus clock */ member
96 struct completion done; /* wake-up from interrupt */
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value) in sifive_spi_write() argument
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
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| D | spi-orion.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
6 * Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/spi/spi.h>
20 #include <linux/clk.h>
74 * have both is for managing the armada-370-spi case with old
96 struct clk *clk; member
97 struct clk *axi_clk;
105 return orion_spi->base + reg; in spi_reg()
130 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
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| D | spi-s3c24xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2009 Simtec Electronics
13 #include <linux/clk.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/spi/s3c24xx.h>
22 #include <linux/spi/s3c24xx-fiq.h>
27 #include "spi-s3c24xx-regs.h"
30 * struct s3c24xx_spi_devstate - per device data
65 void (*set_cs)(struct s3c2410_spi_info *spi,
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| D | spi-meson-spifc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 // Driver for Amlogic Meson SPI flash controller (SPIFC)
8 #include <linux/clk.h>
18 #include <linux/spi/spi.h>
56 #define USER_UC_MASK ((BIT(5) - 1) << 27)
70 * @master: the SPI master
72 * @clk: input clock of the built-in baud rate generator
78 struct clk *clk; member
90 * meson_spifc_wait_ready() - wait for the current operation to terminate
91 * @spifc: the Meson SPI device
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| D | spi-st-ssc4.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
9 * SPI master mode controller driver, used in STMicroelectronics devices.
12 #include <linux/clk.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/spi_bitbang.h>
55 /* SSC SPI Controller */
57 struct clk *clk; member
60 /* SSC SPI current transaction */
75 if (spi_st->words_remaining > FIFO_SIZE) in ssc_write_tx_fifo()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 1 Binding for MTK SPI controller
4 - compatible: should be one of the following.
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
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| D | nvidia,tegra114-spi.txt | 1 NVIDIA Tegra114 SPI controller.
4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
13 - reset-names : Must include the following entries:
14 - spi
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,kirkwood-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,kirkwood-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx93.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/fsl,imx93-power.h>
11 #include <dt-bindings/thermal/thermal.h>
13 #include "imx93-pinfunc.h"
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
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| /kernel/linux/linux-5.10/drivers/iio/frequency/ |
| D | adf4350.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
5 * Copyright 2012-2013 Analog Devices Inc.
12 #include <linux/spi/spi.h>
19 #include <linux/clk.h>
34 struct spi_device *spi; member
38 struct clk *clk; member
52 * writes. The device is configured via a sequence of SPI writes,
77 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
78 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
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