| /kernel/linux/linux-5.10/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
[all …]
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| D | spi-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
19 #include <linux/spi/spi.h>
23 /* STM32F4 SPI registers */
72 /* STM32F4 SPI Baud Rate min/max divisor */
76 /* STM32H7 SPI registers */
153 /* STM32H7 SPI Master Baud Rate min/max divisor */
157 /* STM32H7 SPI Communication mode */
163 /* SPI Communication type */
[all …]
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| D | spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // SPI init/core code
11 #include <linux/dma-mapping.h>
16 #include <linux/clk/clk-conf.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
38 #include <trace/events/spi.h>
48 struct spi_device *spi = to_spi_device(dev); in spidev_release() local
50 spi_controller_put(spi->controller); in spidev_release()
51 kfree(spi->driver_override); in spidev_release()
[all …]
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| D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // General Purpose SPI multiplexer
10 #include <linux/spi/spi.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
27 * @spi: pointer to the device struct attached to the parent
28 * spi controller
[all …]
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| D | spi-qup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
17 #include <linux/spi/spi.h>
19 #include <linux/dma-mapping.h>
116 #define SPI_MAX_XFER (SZ_64K - 64)
141 int w_size; /* bytes per SPI word */
154 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
172 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
[all …]
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| /kernel/linux/linux-6.6/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
16 eeprom and flash memory, codecs and various other controller
17 chips, analog to digital (and d-to-a) converters, and more.
[all …]
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| D | spi-loongson-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
14 #include <linux/spi/spi.h>
16 #include "spi-loongson.h"
18 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
21 writeb(data, spi->base + reg); in loongson_spi_write_reg()
24 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
26 return readb(spi->base + reg); in loongson_spi_read_reg()
29 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
32 unsigned char mask = (BIT(4) | BIT(0)) << spi_get_chipselect(spi, 0); in loongson_spi_set_cs()
[all …]
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| D | spi-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
20 #include <linux/spi/spi.h>
24 /* STM32F4 SPI registers */
73 /* STM32F4 SPI Baud Rate min/max divisor */
77 /* STM32H7 SPI registers */
149 /* STM32H7 SPI Master Baud Rate min/max divisor */
153 /* STM32H7 SPI Communication mode */
159 /* SPI Communication type */
[all …]
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| D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // General Purpose SPI multiplexer
10 #include <linux/spi/spi.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
27 * @spi: pointer to the device struct attached to the parent
28 * spi controller
[all …]
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| D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
21 #include <linux/spi/spi.h>
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
117 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
119 return readl(spi->regs + reg); in mchp_corespi_read()
122 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
124 writel(val, spi->regs + reg); in mchp_corespi_write()
127 static inline void mchp_corespi_disable(struct mchp_corespi *spi) in mchp_corespi_disable() argument
[all …]
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| D | spi-qup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
16 #include <linux/spi/spi.h>
18 #include <linux/dma-mapping.h>
115 #define SPI_MAX_XFER (SZ_64K - 64)
140 int w_size; /* bytes per SPI word */
153 static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
155 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
171 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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| D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
[all …]
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| D | brcm,bcm63xx-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6348/BCM6358 SPI controller
10 - Jonas Gorski <jonas.gorski@gmail.com>
13 Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband
16 This controller has a limitation that can not keep the chip select line active
17 between the SPI transfers within the same SPI message. This can terminate the
18 transaction to some SPI devices prematurely. The issue can be worked around by
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: "spi-controller.yaml#"
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]
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| D | spi-samsung.txt | 1 * Samsung SPI Controller
3 The Samsung SPI controller is used to interface with various devices such as flash
4 and display controllers using the SPI communication interface.
8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
[all …]
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| /kernel/linux/linux-5.10/drivers/mtd/spi-nor/controllers/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Aspeed flash controllers in SPI mode"
7 This enables support for the Firmware Memory controller (FMC)
8 in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
9 and support for the SPI flash memory controller (SPI) for
10 the host firmware. The implementation only supports SPI NOR.
13 tristate "Hisilicon FMC SPI NOR Flash Controller(SFC)"
17 This enables support for HiSilicon FMC SPI NOR flash controller.
20 tristate "NXP SPI Flash Interface (SPIFI)"
24 Enable support for the NXP LPC SPI Flash Interface controller.
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
40 tristate "MSM8916 APCS Clock Controller"
43 Support for the APCS Clock Controller on msm8916 devices. The
49 tristate "MSM8996 CPU Clock Controller"
54 Support for the CPU clock controller on msm8996 devices.
59 tristate "SDX55 and SDX65 APCS Clock Controller"
63 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The
69 tristate "RPM based Clock Controller"
82 tristate "RPM over SMD based Clock Controller"
104 tristate "APQ8084 Global Clock Controller"
[all …]
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| /kernel/linux/linux-6.6/include/trace/events/ |
| D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define TRACE_SYSTEM spi
13 TP_PROTO(struct spi_controller *controller),
15 TP_ARGS(controller),
22 __entry->bus_num = controller->bus_num;
25 TP_printk("spi%d", (int)__entry->bus_num)
31 TP_PROTO(struct spi_controller *controller),
33 TP_ARGS(controller)
39 TP_PROTO(struct spi_controller *controller),
41 TP_ARGS(controller)
[all …]
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| /kernel/linux/linux-5.10/Documentation/spi/ |
| D | spi-summary.rst | 2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a master/slave configuration.
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI masters use a fourth "chip select" line to activate a given SPI slave
24 in parallel. All SPI slaves support chipselects; they are usually active
29 SPI slave functions are usually not interoperable between vendors
[all …]
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| /kernel/linux/linux-6.6/Documentation/spi/ |
| D | spi-summary.rst | 2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a master/slave configuration.
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI masters use a fourth "chip select" line to activate a given SPI slave
24 in parallel. All SPI slaves support chipselects; they are usually active
29 SPI slave functions are usually not interoperable between vendors
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
32 tristate "MSM8916 APCS Clock Controller"
35 Support for the APCS Clock Controller on msm8916 devices. The
41 tristate "MSM8996 CPU Clock Controller"
45 Support for the CPU clock controller on msm8996 devices.
50 tristate "RPM based Clock Controller"
63 tristate "RPM over SMD based Clock Controller"
85 tristate "APQ8084 Global Clock Controller"
88 Support for the global clock controller on apq8084 devices.
89 Say Y if you want to use peripheral devices such as UART, SPI,
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/mtd/ |
| D | spi-nor.rst | 2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
9 controller operates agnostic of the specific device attached. However, some
10 controllers (such as Freescale's QuadSPI controller) cannot easily handle
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/mtd/ |
| D | spi-nor.rst | 2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
9 controller operates agnostic of the specific device attached. However, some
10 controllers (such as Freescale's QuadSPI controller) cannot easily handle
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | aspeed-smc.txt | 1 * Aspeed Firmware Memory controller
2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
[all …]
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