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/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfoundation-v8-spin-table.dtsi4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Dfoundation-v8-spin-table.dtsi4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
Dselftest_mocs.c1 // SPDX-License-Identifier: MIT
17 struct drm_i915_mocs_table table; member
33 ce->ring_size = SZ_16K; in mocs_context_create()
43 err = -ETIME; in request_add_sync()
49 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
55 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
56 err = -ETIME; in request_add_spin()
69 flags = get_mocs_settings(gt->i915, &arg->table); in live_mocs_init()
71 return -EINVAL; in live_mocs_init()
74 arg->l3cc = &arg->table; in live_mocs_init()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dselftest_mocs.c2 * SPDX-License-Identifier: MIT
30 ce->ring = __intel_context_ring_size(SZ_16K); in mocs_context_create()
40 err = -ETIME; in request_add_sync()
46 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
52 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
53 err = -ETIME; in request_add_spin()
65 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
71 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
88 struct drm_i915_mocs_table table; in live_mocs_init() local
94 flags = get_mocs_settings(gt->i915, &table); in live_mocs_init()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/apple/
Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
[all …]
Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/toshiba/
Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/microchip/
Dsparx5_pcb_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
18 enable-method = "spin-table";
/kernel/linux/linux-6.6/arch/arm64/boot/dts/microchip/
Dsparx5_pcb_common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
18 enable-method = "spin-table";
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
28 compatible = "arm,armv7-timer";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/toshiba/
Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/clk/stm32/
Dclk-stm32-core.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
7 #include <linux/clk-provider.h>
16 u32 *table; member
32 const struct clk_div_table *table; member
98 spinlock_t *lock; /* spin lock */
108 spinlock_t *lock; /* spin lock */
118 spinlock_t *lock; /* spin lock */
130 spinlock_t *lock; /* spin lock */
/kernel/linux/linux-6.6/arch/powerpc/platforms/85xx/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
26 #include <asm/code-patching.h>
58 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase()
61 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase()
62 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase()
66 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase()
91 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase()
122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self()
131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/85xx/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
26 #include <asm/code-patching.h>
58 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase()
61 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase()
62 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase()
66 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase()
91 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase()
122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self()
131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self()
[all …]
/kernel/linux/linux-6.6/Documentation/hwmon/
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]

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