Home
last modified time | relevance | path

Searched full:spll (Results 1 – 25 of 108) sorted by relevance

12345

/kernel/linux/linux-5.10/drivers/clk/uniphier/
Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
57 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
[all …]
/kernel/linux/linux-6.6/drivers/clk/uniphier/
Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Dradeon_clocks.c42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dradeon_clocks.c42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx31.c34 static const char *mcu_main_sel[] = { "spll", "mpll", };
36 static const char *csi_sel[] = { "upll", "spll", };
37 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
70 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
98 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); in _mx31_clocks_init()
118 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); in _mx31_clocks_init()
Dclk-imx7ulp.c24 static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
82 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600); in imx7ulp_clk_scg1_init()
90 /* SPLL PFDs */ in imx7ulp_clk_scg1_init()
91 hws[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0); in imx7ulp_clk_scg1_init()
92 hws[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1); in imx7ulp_clk_scg1_init()
93 hws[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2); in imx7ulp_clk_scg1_init()
94 hws[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3); in imx7ulp_clk_scg1_init()
Dclk-imx27.c34 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
40 "ckih_gate", "mpll", "spll", "cpu_div",
65 clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); in _mx27_clocks_init()
66 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx27_clocks_init()
Dclk-imx1.c49 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in mx1_clocks_init_dt()
50 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx1_clocks_init_dt()
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-imx31.c33 static const char *mcu_main_sel[] = { "spll", "mpll", };
35 static const char *csi_sel[] = { "upll", "spll", };
36 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
87 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); in _mx31_clocks_init()
107 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); in _mx31_clocks_init()
Dclk-imx7ulp.c24 static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
82 …hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600… in imx7ulp_clk_scg1_init()
90 /* SPLL PFDs */ in imx7ulp_clk_scg1_init()
91 …hws[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd0", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
92 …hws[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd1", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
93 …hws[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd2", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
94 …hws[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd3", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
Dclk-imx27.c33 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
39 "ckih_gate", "mpll", "spll", "cpu_div",
64 clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); in _mx27_clocks_init()
65 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx27_clocks_init()
Dclk-imx1.c48 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in mx1_clocks_init_dt()
49 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx1_clocks_init_dt()
/kernel/linux/linux-5.10/drivers/clk/microchip/
Dclk-core.c75 /* SoC specific clock needed during SPLL clock rate switch */
628 pr_warn("spll: no match found\n"); in spll_calc_mult_div()
689 * We can't change SPLL counters when it is in-active use in spll_clk_set_rate()
725 /* SPLL clock operation */
735 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
739 if (!spll) in pic32_spll_clk_register()
742 spll->core = core; in pic32_spll_clk_register()
743 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
744 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
[all …]
/kernel/linux/linux-6.6/drivers/clk/microchip/
Dclk-core.c75 /* SoC specific clock needed during SPLL clock rate switch */
628 pr_warn("spll: no match found\n"); in spll_calc_mult_div()
689 * We can't change SPLL counters when it is in-active use in spll_clk_set_rate()
725 /* SPLL clock operation */
735 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
739 if (!spll) in pic32_spll_clk_register()
742 spll->core = core; in pic32_spll_clk_register()
743 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
744 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgpu_atomfirmware.c380 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
418 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
420 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
421 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
422 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
423 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
424 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
425 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
426 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
427 spll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
Damdgpu_atombios.c570 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
616 spll->reference_freq = in amdgpu_atombios_get_clock_info()
618 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
620 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
622 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
626 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
627 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
629 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
631 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
634 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_atomfirmware.c674 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
709 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
711 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
713 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
714 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
715 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
716 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
717 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
718 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
719 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
[all …]
Damdgpu_atombios.c570 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
616 spll->reference_freq = in amdgpu_atombios_get_clock_info()
618 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
620 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
622 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
626 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
627 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
629 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
631 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
634 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv40.c36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
Dnv50.c467 /* shader: tie to nvclk if possible, otherwise use spll. have to be in nv50_clk_calc()
474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
483 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv40.c36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
/kernel/linux/linux-6.6/arch/mips/pic32/pic32mzda/
Dearly_clk.c18 #define SPLL 1 macro
71 case SPLL: in pic32_get_sysclk()
/kernel/linux/linux-5.10/arch/mips/pic32/pic32mzda/
Dearly_clk.c18 #define SPLL 1 macro
71 case SPLL: in pic32_get_sysclk()
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dpm-imx27.c30 /* Clear MPEN and SPEN to disable MPLL/SPLL */ in mx27_suspend_enter()
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dpm-imx27.c29 /* Clear MPEN and SPEN to disable MPLL/SPLL */ in mx27_suspend_enter()

12345