| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | ti,cdce925.txt | 6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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| D | mediatek,mt8186-fhctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek frequency hopping and spread spectrum clocking control
10 - Edward-JW Yang <edward-jw.yang@mediatek.com>
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
20 - mediatek,mt6795-fhctl
21 - mediatek,mt8173-fhctl
22 - mediatek,mt8186-fhctl
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| D | renesas,9series.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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| D | nuvoton,ma35d1-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chi-Fang Li <cfli0@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
18 include/dt-bindings/clock/ma35d1-clk.h
23 - const: nuvoton,ma35d1-clk
28 "#clock-cells":
34 nuvoton,pll-mode:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/ |
| D | dpll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-platform-dptf | 4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-acpi@vger.kernel.org
19 Contact: linux-acpi@vger.kernel.org
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-acpi@vger.kernel.org
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| /kernel/linux/linux-6.6/Documentation/driver-api/thermal/ |
| D | intel_dptf.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/ |
| D | imx-sata.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
31 - description: sata clock
32 - description: sata reference clock
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | imx-sata.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
31 - description: sata clock
32 - description: sata reference clock
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| /kernel/linux/linux-6.6/Documentation/misc-devices/ |
| D | ics932s401.rst | 18 -----------
22 This chip has 4 clock outputs--a base clock for the CPU (which is likely
25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
33 ----------------
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| /kernel/linux/linux-5.10/Documentation/misc-devices/ |
| D | ics932s401.rst | 18 -----------
22 This chip has 4 clock outputs--a base clock for the CPU (which is likely
25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
33 ----------------
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu11_driver_if_sienna_cichlid.h | 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-renesas-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
14 #include <linux/clk-provider.h>
54 /* Supported Renesas 9-series models. */
60 /* Structure to describe features of a particular 9-series model */
78 * Renesas 9-series i2c regmap
114 return -EIO; in rs9_regmap_i2c_write()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 2 * Copyright 2012-16 Advanced Micro Devices, Inc.
36 /*ClocksStateInvalid - should not be used*/
38 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
48 * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
51 * Reads from VBIOS the XGMI spread spectrum info and saves it within
54 * sets the ->xgmi_enabled flag.
60 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; in dce121_clock_patch_xgmi_ss_info()
62 clk_mgr_dce->xgmi_enabled = false; in dce121_clock_patch_xgmi_ss_info()
64 result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, in dce121_clock_patch_xgmi_ss_info()
67 clk_mgr_dce->xgmi_enabled = true; in dce121_clock_patch_xgmi_ss_info()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 2 * Copyright 2012-16 Advanced Micro Devices, Inc.
36 /*ClocksStateInvalid - should not be used*/
38 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
48 * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
51 * Reads from VBIOS the XGMI spread spectrum info and saves it within
54 * sets the ->xgmi_enabled flag.
60 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; in dce121_clock_patch_xgmi_ss_info()
62 clk_mgr_dce->xgmi_enabled = false; in dce121_clock_patch_xgmi_ss_info()
64 result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, in dce121_clock_patch_xgmi_ss_info()
67 clk_mgr_dce->xgmi_enabled = true; in dce121_clock_patch_xgmi_ss_info()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/ |
| D | dfp.c | 5 * Copyright 2007-2009 Stuart Bennett
58 * this does not give a correct answer for off-chip dvi, but there's no in nv04_dfp_get_bound_head()
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_get_bound_head()
72 * Luckily we do know the values ;-) in nv04_dfp_bind_head()
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_bind_head()
84 if (dcbent->type == DCB_OUTPUT_LVDS) in nv04_dfp_bind_head()
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); in nv04_dfp_bind_head()
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); in nv04_dfp_bind_head()
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
115 struct drm_device *dev = encoder->dev; in nv04_dfp_update_fp_control()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/ |
| D | dfp.c | 5 * Copyright 2007-2009 Stuart Bennett
58 * this does not give a correct answer for off-chip dvi, but there's no in nv04_dfp_get_bound_head()
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_get_bound_head()
72 * Luckily we do know the values ;-) in nv04_dfp_bind_head()
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_bind_head()
84 if (dcbent->type == DCB_OUTPUT_LVDS) in nv04_dfp_bind_head()
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); in nv04_dfp_bind_head()
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); in nv04_dfp_bind_head()
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
115 struct drm_device *dev = encoder->dev; in nv04_dfp_update_fp_control()
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| /kernel/linux/linux-6.6/drivers/phy/starfive/ |
| D | phy-jh7110-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
66 writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); in phy_usb3_mode_set()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu11_driver_if_sienna_cichlid.h | 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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| /kernel/linux/linux-6.6/drivers/phy/rockchip/ |
| D | phy-rockchip-naneng-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
156 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
158 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
166 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
167 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
168 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
170 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
175 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
178 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
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| /kernel/linux/linux-5.10/drivers/scsi/isci/ |
| D | probe_roms.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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| /kernel/linux/linux-6.6/drivers/scsi/isci/ |
| D | probe_roms.h | 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | brcm-sata-phy.txt | 4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
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| /kernel/linux/linux-6.6/include/linux/phy/ |
| D | phy-dp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
51 * Pre-emphasis levels, as specified by DisplayPort specification, to be
61 * Flag indicating, whether or not to enable spread-spectrum clocking.
88 * and pre-emphasis to requested values. Only lanes specified
|