Home
last modified time | relevance | path

Searched +full:sram +full:- +full:section (Results 1 – 25 of 157) sorted by relevance

1234567

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
[all …]
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
[all …]
/kernel/liteos_a/kernel/include/
Dlos_builddef.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
55 #define LITE_OS_SEC_TEXT /* __attribute__((section(".text.sram"))) */
59 #define LITE_OS_SEC_TEXT_MINOR /* __attribute__((section(".text.ddr"))) */
63 #define LITE_OS_SEC_TEXT_INIT /* __attribute__((section(".text.init"))) */
67 #define LITE_OS_SEC_DATA /* __attribute__((section(".data.sram"))) */
71 #define LITE_OS_SEC_DATA_MINOR /* __attribute__((section(".data.ddr"))) */
75 #define LITE_OS_SEC_DATA_INIT /* __attribute__((section(".data.init"))) */
79 #define LITE_OS_SEC_BSS /* __attribute__((section(".bss.sram"))) */
83 #define LITE_OS_SEC_BSS_MINOR /* __attribute__((section(".bss.ddr"))) */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
31 - description: SCMI compliant firmware with mailbox transport
33 - const: arm,scmi
34 - description: SCMI compliant firmware with ARM SMC/HVC transport
36 - const: arm,scmi-smc
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
38 with shmem address(4KB-page, offset) as parameters
[all …]
Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
38 - const: arm,scpi-pre-1.0
[all …]
/kernel/liteos_m/utils/
Dlos_compiler.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
202 * Vector table section
205 #define LITE_OS_SEC_VEC __attribute__ ((section(".vector")))
210 * .Text section (Code section)
213 #define LITE_OS_SEC_TEXT // __attribute__((section(".sram.text")))
218 * .Text.ddr section
221 #define LITE_OS_SEC_TEXT_MINOR // __attribute__((section(".dyn.text")))
226 * .Text.init section
229 #define LITE_OS_SEC_TEXT_INIT // __attribute__((section(".dyn.text")))
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
/kernel/linux/linux-5.10/drivers/memory/
Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/kernel/linux/linux-6.6/drivers/memory/
Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-6.6/drivers/input/touchscreen/
Dgoodix_fwupload.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (c) 2010 - 2012 Goodix Technology.
54 if (fw->size != expected_size) { in goodix_firmware_verify()
56 expected_size, fw->size); in goodix_firmware_verify()
57 return -EINVAL; in goodix_firmware_verify()
60 data = fw->data + GOODIX_FW_HEADER_LENGTH; in goodix_firmware_verify()
64 return -EINVAL; in goodix_firmware_verify()
71 return -EINVAL; in goodix_firmware_verify()
74 fw_header = (const struct goodix_fw_header *)fw->data; in goodix_firmware_verify()
76 fw_header->hw_info[0], fw_header->hw_info[1], in goodix_firmware_verify()
[all …]
/kernel/liteos_m/tools/
Dmem_analysis.py2 # -*- coding: utf-8 -*-
5 # Copyright (c) 2020-2022 Huawei Device Co., Ltd.
10 # http://www.apache.org/licenses/LICENSE-2.0
45 def storage_static_data(offset, section, sizeHex, symbol, lib, obj): argument
48 static_map[g_row_num] = {'offsets' : "offsets", 'section' : "section",\
54 static_map[g_row_num] = {'offsets': offset, 'section' : section,\
66 c.value = values.get('section')
77 wb.save('static_symbol-%s.xlsx' % datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
86 target_list.append('{:<30s}'.format(values.get('section')))
155 wb.save('dync_mem-%s.xlsx' % datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-rockchip/
Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/kernel/linux/linux-6.6/arch/arm/mach-rockchip/
Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/kernel/linux/linux-5.10/arch/csky/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
276 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
281 int "Maximum number of CPUs (2-32)"
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/
Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/kernel/linux/linux-6.6/Documentation/driver-api/memory-devices/
Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed

1234567