| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() local
60 switch (device->chipset) { in read_pll_src()
73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); in read_pll_src()
74 ref *= (coef & 0x01000000) ? 2 : 4; in read_pll_src()
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
76 N = ((coef & 0x0000ff00) >> 8) + 1; in read_pll_src()
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| D | nv40.c | 42 struct nvkm_device *device = clk->base.subdev.device; in read_pll_1()
58 struct nvkm_device *device = clk->base.subdev.device; in read_pll_2()
60 u32 coef = nvkm_rd32(device, reg + 0x04); in read_pll_2() local
61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2()
63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2()
64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
84 switch (src) { in read_clk()
97 nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in nv40_clk_read() argument
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| D | gf100.c | 38 u32 coef; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
63 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
64 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
65 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
66 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
75 sclk = device->crystal; in read_pll()
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| D | gk104.c | 38 u32 coef; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
77 sclk = device->crystal; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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| D | gt215.c | 45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
117 u32 coef = nvkm_rd32(device, pll + 4); in read_pll() local
118 M = (coef & 0x000000ff) >> 0; in read_pll()
119 N = (coef & 0x0000ff00) >> 8; in read_pll()
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| D | mcp77.c | 44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); in read_pll() local
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
89 switch (src) { in mcp77_clk_read()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv50.c | 34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() local
60 switch (device->chipset) { in read_pll_src()
73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); in read_pll_src()
74 ref *= (coef & 0x01000000) ? 2 : 4; in read_pll_src()
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
76 N = ((coef & 0x0000ff00) >> 8) + 1; in read_pll_src()
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| D | nv40.c | 42 struct nvkm_device *device = clk->base.subdev.device; in read_pll_1()
58 struct nvkm_device *device = clk->base.subdev.device; in read_pll_2()
60 u32 coef = nvkm_rd32(device, reg + 0x04); in read_pll_2() local
61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2()
63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2()
64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
84 switch (src) { in read_clk()
97 nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in nv40_clk_read() argument
[all …]
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| D | gf100.c | 38 u32 coef; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
63 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
64 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
65 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
66 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
75 sclk = device->crystal; in read_pll()
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| D | gk104.c | 38 u32 coef; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
77 sclk = device->crystal; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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| D | gt215.c | 45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
117 u32 coef = nvkm_rd32(device, pll + 4); in read_pll() local
118 M = (coef & 0x000000ff) >> 0; in read_pll()
119 N = (coef & 0x0000ff00) >> 8; in read_pll()
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| D | mcp77.c | 44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); in read_pll() local
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
89 switch (src) { in mcp77_clk_read()
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| /kernel/linux/linux-6.6/drivers/media/platform/st/sti/bdisp/ |
| D | bdisp-hw.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "bdisp-filter.h"
11 #include "bdisp-reg.h"
27 bool cconv; /* RGB - YUV conversion */
34 bool src_interlaced; /* is the src an interlaced buffer */
35 u8 src_nbp; /* nb of planes of the src */
36 bool src_yuv; /* is the src a YUV color format */
37 bool src_420; /* is the src 4:2:0 chroma subsampled */
54 .coef = {
68 .coef = {
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/sti/bdisp/ |
| D | bdisp-hw.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "bdisp-filter.h"
11 #include "bdisp-reg.h"
27 bool cconv; /* RGB - YUV conversion */
34 bool src_interlaced; /* is the src an interlaced buffer */
35 u8 src_nbp; /* nb of planes of the src */
36 bool src_yuv; /* is the src a YUV color format */
37 bool src_420; /* is the src 4:2:0 chroma subsampled */
54 .coef = {
68 .coef = {
[all …]
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| /kernel/linux/linux-6.6/drivers/dma/ioat/ |
| D | prep.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2004 - 2015 Intel Corporation.
10 #include <linux/dma-mapping.h>
36 raw->field[xor_idx_to_field[idx]] = addr + offset; in xor_set_src()
43 return raw->field[pq_idx_to_field[idx]]; in pq_get_src()
50 return raw->field[pq16_idx_to_field[idx]]; in pq16_get_src()
54 dma_addr_t addr, u32 offset, u8 coef, int idx) in pq_set_src() argument
59 raw->field[pq_idx_to_field[idx]] = addr + offset; in pq_set_src()
60 pq->coef[idx] = coef; in pq_set_src()
64 dma_addr_t addr, u32 offset, u8 coef, unsigned idx) in pq16_set_src() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/dma/ioat/ |
| D | prep.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2004 - 2015 Intel Corporation.
10 #include <linux/dma-mapping.h>
36 raw->field[xor_idx_to_field[idx]] = addr + offset; in xor_set_src()
43 return raw->field[pq_idx_to_field[idx]]; in pq_get_src()
50 return raw->field[pq16_idx_to_field[idx]]; in pq16_get_src()
54 dma_addr_t addr, u32 offset, u8 coef, int idx) in pq_set_src() argument
59 raw->field[pq_idx_to_field[idx]] = addr + offset; in pq_set_src()
60 pq->coef[idx] = coef; in pq_set_src()
64 dma_addr_t addr, u32 offset, u8 coef, unsigned idx) in pq16_set_src() argument
[all …]
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| /kernel/linux/linux-5.10/crypto/async_tx/ |
| D | async_raid6_recov.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Asynchronous RAID-6 recovery calculations ASYNC_TX API.
12 #include <linux/dma-mapping.h>
19 struct page **srcs, unsigned int *src_offs, unsigned char *coef, in async_sum_product() argument
24 struct dma_device *dma = chan ? chan->device : NULL; in async_sum_product()
31 unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT); in async_sum_product()
34 struct device *dev = dma->dev; in async_sum_product()
39 if (submit->flags & ASYNC_TX_FENCE) in async_sum_product()
41 unmap->addr[0] = dma_map_page(dev, srcs[0], src_offs[0], in async_sum_product()
43 unmap->addr[1] = dma_map_page(dev, srcs[1], src_offs[1], in async_sum_product()
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| /kernel/linux/linux-6.6/crypto/async_tx/ |
| D | async_raid6_recov.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Asynchronous RAID-6 recovery calculations ASYNC_TX API.
12 #include <linux/dma-mapping.h>
19 struct page **srcs, unsigned int *src_offs, unsigned char *coef, in async_sum_product() argument
24 struct dma_device *dma = chan ? chan->device : NULL; in async_sum_product()
31 unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT); in async_sum_product()
34 struct device *dev = dma->dev; in async_sum_product()
39 if (submit->flags & ASYNC_TX_FENCE) in async_sum_product()
41 unmap->addr[0] = dma_map_page(dev, srcs[0], src_offs[0], in async_sum_product()
43 unmap->addr[1] = dma_map_page(dev, srcs[1], src_offs[1], in async_sum_product()
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| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | ac100.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
91 #define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */
92 #define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */
93 #define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */
94 #define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */
100 #define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */
101 #define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */
102 #define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */
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| /kernel/linux/linux-6.6/include/linux/mfd/ |
| D | ac100.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
91 #define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */
92 #define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */
93 #define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */
94 #define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */
100 #define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */
101 #define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */
102 #define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | phy-mtk-xsphy.txt | 1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | mediatek,xsphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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| /kernel/linux/linux-5.10/sound/pci/hda/ |
| D | patch_cirrus.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
65 /* Vendor-specific processing widget */
72 /* coef indices */
78 * 1 = digital immediate, analog zero-cross
79 * 2 = digtail & analog soft-ramp
80 * 3 = digital soft-ramp, analog zero-cross
84 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
85 /* PGA mode: 0 = differential, 1 = signle-ended */
87 #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */
91 * 1 = zero-cross
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| /kernel/linux/linux-6.6/sound/pci/hda/ |
| D | patch_cirrus.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
66 /* Vendor-specific processing widget */
73 /* coef indices */
79 * 1 = digital immediate, analog zero-cross
80 * 2 = digtail & analog soft-ramp
81 * 3 = digital soft-ramp, analog zero-cross
85 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
86 /* PGA mode: 0 = differential, 1 = signle-ended */
88 #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */
92 * 1 = zero-cross
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | fsl_raid.c | 13 * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
66 #include <linux/dma-mapping.h>
85 /* Add descriptors into per chan software queue - submit_q */
94 re_chan = container_of(tx->chan, struct fsl_re_chan, chan); in fsl_re_tx_submit()
96 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
98 list_add_tail(&desc->node, &re_chan->submit_q); in fsl_re_tx_submit()
99 spin_unlock_irqrestore(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
114 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_issue_pending()
116 in_be32(&re_chan->jrregs->inbring_slot_avail)); in fsl_re_issue_pending()
118 list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) { in fsl_re_issue_pending()
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