| /kernel/linux/linux-5.10/arch/mips/bcm63xx/ |
| D | clk.c | 28 static DEFINE_MUTEX(clocks_mutex);
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked()
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument
48 if (enable) in bcm_hwclock_set()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
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| /kernel/linux/linux-6.6/arch/mips/bcm63xx/ |
| D | clk.c | 28 static DEFINE_MUTEX(clocks_mutex);
31 static void clk_enable_unlocked(struct clk *clk) in clk_enable_unlocked()
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
37 static void clk_disable_unlocked(struct clk *clk) in clk_disable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
43 static void bcm_hwclock_set(u32 mask, int enable) in bcm_hwclock_set() argument
48 if (enable) in bcm_hwclock_set()
58 static void enet_misc_set(struct clk *clk, int enable) in enet_misc_set() argument
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/kernel/ |
| D | security.c | 1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/asm-prototypes.h>
17 #include <asm/code-patching.h>
32 static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
33 static enum branch_cache_flush_type link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
36 static bool no_nospec;
37 static bool btb_flush_enabled;
39 static bool no_spectrev2;
42 static void enable_barrier_nospec(bool enable) in enable_barrier_nospec() argument
44 barrier_nospec_enabled = enable; in enable_barrier_nospec()
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| /kernel/linux/linux-6.6/arch/mips/alchemy/common/ |
| D | usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
29 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
30 #define USBHEN_E (1 << 2) /* OHCI block enable */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
35 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
40 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
41 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
42 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
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| /kernel/linux/linux-5.10/arch/mips/alchemy/common/ |
| D | usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
29 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */
30 #define USBHEN_E (1 << 2) /* OHCI block enable */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
35 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */
40 #define USBCFG_UCE (1 << 18) /* UDC clock enable */
41 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */
42 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */
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| /kernel/linux/linux-6.6/drivers/clk/pxa/ |
| D | clk-pxa3xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
30 #define CKENA (0x000C) /* A Clock Enable Register */
31 #define CKENB (0x0010) /* B Clock Enable Register */
32 #define CKENC (0x0024) /* C Clock Enable Register */
38 #define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | security.c | 1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/asm-prototypes.h>
15 #include <asm/code-patching.h>
29 static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
30 static enum branch_cache_flush_type link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
33 static bool no_nospec;
34 static bool btb_flush_enabled;
36 static bool no_spectrev2;
39 static void enable_barrier_nospec(bool enable) in enable_barrier_nospec() argument
41 barrier_nospec_enabled = enable; in enable_barrier_nospec()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-sr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
34 static const struct iproc_pll_ctrl sr_genpll0 = {
47 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
57 .enable = ENABLE_VAL(0x4, 7, 1, 13),
63 .enable = ENABLE_VAL(0x4, 8, 2, 14),
69 .enable = ENABLE_VAL(0x4, 9, 3, 15),
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| D | clk-ns2.c | 16 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/bcm-ns2.h>
22 #include "clk-iproc.h"
41 static const struct iproc_pll_ctrl genpll_scr = {
53 static const struct iproc_clk_ctrl genpll_scr_clk[] = {
61 .enable = ENABLE_VAL(0x0, 18, 12, 0),
67 .enable = ENABLE_VAL(0x0, 19, 13, 0),
73 .enable = ENABLE_VAL(0x0, 20, 14, 0),
79 .enable = ENABLE_VAL(0x0, 21, 15, 0),
85 .enable = ENABLE_VAL(0x0, 22, 16, 0),
[all …]
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| D | clk-cygnus.c | 16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
51 static void __init cygnus_armpll_init(struct device_node *node) in cygnus_armpll_init()
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
57 static const struct iproc_pll_ctrl genpll = {
71 static const struct iproc_clk_ctrl genpll_clk[] = {
75 .enable = ENABLE_VAL(0x4, 6, 0, 12),
81 .enable = ENABLE_VAL(0x4, 7, 1, 13),
87 .enable = ENABLE_VAL(0x4, 8, 2, 14),
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/bcm/ |
| D | clk-sr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
34 static const struct iproc_pll_ctrl sr_genpll0 = {
47 static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
51 .enable = ENABLE_VAL(0x4, 6, 0, 12),
57 .enable = ENABLE_VAL(0x4, 7, 1, 13),
63 .enable = ENABLE_VAL(0x4, 8, 2, 14),
69 .enable = ENABLE_VAL(0x4, 9, 3, 15),
[all …]
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| D | clk-ns2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
31 static const struct iproc_pll_ctrl genpll_scr = {
43 static const struct iproc_clk_ctrl genpll_scr_clk[] = {
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
57 .enable = ENABLE_VAL(0x0, 19, 13, 0),
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
69 .enable = ENABLE_VAL(0x0, 21, 15, 0),
[all …]
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| D | clk-cygnus.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
41 static void __init cygnus_armpll_init(struct device_node *node) in cygnus_armpll_init()
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
47 static const struct iproc_pll_ctrl genpll = {
61 static const struct iproc_clk_ctrl genpll_clk[] = {
65 .enable = ENABLE_VAL(0x4, 6, 0, 12),
71 .enable = ENABLE_VAL(0x4, 7, 1, 13),
[all …]
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| /kernel/linux/linux-6.6/drivers/media/platform/ti/davinci/ |
| D | vpif.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
129 static inline void vpif_set_bit(u32 reg, u32 bit) in vpif_set_bit()
134 static inline void vpif_clr_bit(u32 reg, u32 bit) in vpif_clr_bit()
145 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
183 /* bit position of clock and channel enable in vpif_chn_ctrl register */
262 /* inline function to enable/disable channel0 */
263 static inline void enable_channel0(int enable) in enable_channel0() argument
265 if (enable) in enable_channel0()
271 /* inline function to enable/disable channel1 */
[all …]
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| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | altera-hps2fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
49 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show()
51 struct altera_hps2fpga_data *priv = bridge->priv; in alt_hps2fpga_enable_show()
53 return reset_control_status(priv->bridge_reset); in alt_hps2fpga_enable_show()
57 static unsigned int l3_remap_shadow;
[all …]
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | altera-hps2fpga.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
49 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show()
51 struct altera_hps2fpga_data *priv = bridge->priv; in alt_hps2fpga_enable_show()
53 return reset_control_status(priv->bridge_reset); in alt_hps2fpga_enable_show()
57 static unsigned int l3_remap_shadow;
[all …]
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| /kernel/linux/linux-6.6/drivers/accel/ivpu/ |
| D | ivpu_hw_37xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
63 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
73 static char *ivpu_platform_to_str(u32 platform) in ivpu_platform_to_str()
87 static void ivpu_hw_read_platform(struct ivpu_device *vdev) in ivpu_hw_read_platform()
93 vdev->platform = platform; in ivpu_hw_read_platform()
95 vdev->platform = IVPU_PLATFORM_SILICON; in ivpu_hw_read_platform()
98 ivpu_platform_to_str(vdev->platform), vdev->platform); in ivpu_hw_read_platform()
101 static void ivpu_hw_wa_init(struct ivpu_device *vdev) in ivpu_hw_wa_init()
103 vdev->wa.punit_disabled = ivpu_is_fpga(vdev); in ivpu_hw_wa_init()
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| D | ivpu_hw_40xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-2023 Intel Corporation
68 #define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)
78 static char *ivpu_platform_to_str(u32 platform) in ivpu_platform_to_str()
92 static const struct dmi_system_id ivpu_dmi_platform_simulation[] = {
110 static void ivpu_hw_read_platform(struct ivpu_device *vdev) in ivpu_hw_read_platform()
113 vdev->platform = IVPU_PLATFORM_SIMICS; in ivpu_hw_read_platform()
115 vdev->platform = IVPU_PLATFORM_SILICON; in ivpu_hw_read_platform()
118 ivpu_platform_to_str(vdev->platform), vdev->platform); in ivpu_hw_read_platform()
121 static void ivpu_hw_wa_init(struct ivpu_device *vdev) in ivpu_hw_wa_init()
[all …]
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | ab8500-codec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
8 * for ST-Ericsson.
14 * for ST-Ericsson.
31 #include <linux/mfd/abx500/ab8500-sysctrl.h>
32 #include <linux/mfd/abx500/ab8500-codec.h>
41 #include <sound/soc-dapm.h>
44 #include "ab8500-codec.h"
58 /* Nr of FIR/IIR-coeff banks in ANC-block */
79 static const char * const enum_sid_state[] = {
[all …]
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| /kernel/linux/linux-6.6/sound/soc/codecs/ |
| D | ab8500-codec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
8 * for ST-Ericsson.
14 * for ST-Ericsson.
29 #include <linux/mfd/abx500/ab8500-sysctrl.h>
30 #include <linux/mfd/abx500/ab8500-codec.h>
39 #include <sound/soc-dapm.h>
42 #include "ab8500-codec.h"
56 /* Nr of FIR/IIR-coeff banks in ANC-block */
77 static const char * const enum_sid_state[] = {
[all …]
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| D | nau8315.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8315.c -- NAU8315 ALSA SoC Audio Amplifier Driver
22 #include <sound/soc-dai.h>
23 #include <sound/soc-dapm.h>
26 struct gpio_desc *enable; member
30 static int nau8315_daiops_trigger(struct snd_pcm_substream *substream, in nau8315_daiops_trigger()
33 struct snd_soc_component *component = dai->component; in nau8315_daiops_trigger()
37 if (!nau8315->enable) in nau8315_daiops_trigger()
44 if (nau8315->enpin_switch) { in nau8315_daiops_trigger()
45 gpiod_set_value(nau8315->enable, 1); in nau8315_daiops_trigger()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/platform/davinci/ |
| D | vpif.h | 4 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
137 static inline void vpif_set_bit(u32 reg, u32 bit) in vpif_set_bit()
142 static inline void vpif_clr_bit(u32 reg, u32 bit) in vpif_clr_bit()
153 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
191 /* bit position of clock and channel enable in vpif_chn_ctrl register */
270 /* inline function to enable/disable channel0 */
271 static inline void enable_channel0(int enable) in enable_channel0() argument
273 if (enable) in enable_channel0()
279 /* inline function to enable/disable channel1 */
280 static inline void enable_channel1(int enable) in enable_channel1() argument
[all …]
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| /kernel/linux/linux-6.6/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-gpio.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-gpio.c -- Mediatek 8192 afe gpio ctrl
12 #include "mt8192-afe-common.h"
13 #include "mt8192-afe-gpio.h"
15 static struct pinctrl *aud_pinctrl;
61 static struct audio_gpio_attr aud_gpios[MT8192_AFE_GPIO_GPIO_NUM] = {
102 static DEFINE_MUTEX(gpio_request_mutex);
104 static int mt8192_afe_gpio_select(struct device *dev, in mt8192_afe_gpio_select()
112 return -EINVAL; in mt8192_afe_gpio_select()
118 return -EIO; in mt8192_afe_gpio_select()
[all …]
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| /kernel/linux/linux-6.6/drivers/fpga/tests/ |
| D | fpga-bridge-test.c | 1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/fpga/fpga-bridge.h>
17 bool enable; member
26 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
28 struct bridge_stats *stats = bridge->priv; in op_enable_set()
30 stats->enable = enable; in op_enable_set()
39 static const struct fpga_bridge_ops fake_bridge_ops = {
44 * register_test_bridge() - Register a fake FPGA bridge for testing.
49 static struct bridge_ctx *register_test_bridge(struct kunit *test) in register_test_bridge()
56 ctx->pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, NULL, 0); in register_test_bridge()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | ih_v6_1.c | 37 static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
46 static void ih_v6_1_init_register_offset(struct amdgpu_device *adev) in ih_v6_1_init_register_offset()
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
[all …]
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