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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 by a regular node for the SRAM controller itself, with sub-nodes
19 "#address-cells":
22 "#size-cells":
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 by a regular node for the SRAM controller itself, with sub-nodes
19 "#address-cells":
22 "#size-cells":
[all …]
/kernel/linux/linux-6.6/drivers/soc/sunxi/
Dsunxi_sram.c6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
91 .compatible = "allwinner,sun4i-a10-sram-c1",
95 .compatible = "allwinner,sun4i-a10-sram-d",
99 .compatible = "allwinner,sun50i-a64-sram-c",
120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()
122 for_each_child_of_node(sram_dev->of_node, sram_node) { in sunxi_sram_show()
123 if (!of_device_is_compatible(sram_node, "mmio-sram")) in sunxi_sram_show()
[all …]
/kernel/linux/linux-5.10/drivers/soc/sunxi/
Dsunxi_sram.c6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),
87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",
91 .compatible = "allwinner,sun4i-a10-sram-c1",
95 .compatible = "allwinner,sun4i-a10-sram-d",
99 .compatible = "allwinner,sun50i-a64-sram-c",
120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()
122 for_each_child_of_node(sram_dev->of_node, sram_node) { in sunxi_sram_show()
132 sram_data = match->data; in sunxi_sram_show()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
[all …]
Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/clock/sun8i-tcon-top.h>
49 #include <dt-bindings/reset/sun8i-r40-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/thermal/thermal.h>
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
[all …]
Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
[all …]
Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
[all …]
Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/clock/sun8i-tcon-top.h>
48 #include <dt-bindings/reset/sun8i-r40-ccu.h>
49 #include <dt-bindings/reset/sun8i-de2.h>
50 #include <dt-bindings/thermal/thermal.h>
53 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/crypto/allwinner/sun4i-ss/
Dsun4i-ss-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
24 #include "sun4i-ss.h"
50 .cra_driver_name = "md5-sun4i-ss",
77 .cra_driver_name = "sha1-sun4i-ss",
99 .cra_driver_name = "cbc-aes-sun4i-ss",
120 .cra_driver_name = "ecb-aes-sun4i-ss",
142 .cra_driver_name = "cbc-des-sun4i-ss",
163 .cra_driver_name = "ecb-des-sun4i-ss",
[all …]
/kernel/linux/linux-6.6/drivers/crypto/allwinner/sun4i-ss/
Dsun4i-ss-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
24 #include "sun4i-ss.h"
50 .cra_driver_name = "md5-sun4i-ss",
77 .cra_driver_name = "sha1-sun4i-ss",
99 .cra_driver_name = "cbc-aes-sun4i-ss",
120 .cra_driver_name = "ecb-aes-sun4i-ss",
142 .cra_driver_name = "cbc-des-sun4i-ss",
163 .cra_driver_name = "ecb-des-sun4i-ss",
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]
/kernel/linux/linux-6.6/drivers/ata/
Dahci_sunxi.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DRV_NAME "ahci-sunxi"
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
150 struct ahci_host_priv *hpriv = ap->host->private_data; in ahci_sunxi_start_engine()
156 * User's Guide document (TMS320C674x/OMAP-L1x Processor in ahci_sunxi_start_engine()
158 * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR), in ahci_sunxi_start_engine()
173 * transmit (system bus read, device write) operation. [...] in ahci_sunxi_start_engine()
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dahci_sunxi.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define DRV_NAME "ahci-sunxi"
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
150 struct ahci_host_priv *hpriv = ap->host->private_data; in ahci_sunxi_start_engine()
156 * User's Guide document (TMS320C674x/OMAP-L1x Processor in ahci_sunxi_start_engine()
158 * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR), in ahci_sunxi_start_engine()
173 * transmit (system bus read, device write) operation. [...] in ahci_sunxi_start_engine()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/allwinner/
Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
33 #include "sun4i-emac.h"
35 #define DRV_NAME "sun4i-emac"
40 static int debug = -1; /* defaults above */;
51 * The EMAC uses an address register to control where data written
56 * protect the system, but the calls themselves save the address
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
100 if (db->speed == SPEED_100) in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
[all …]
/kernel/linux/linux-6.6/Documentation/admin-guide/media/
Dcec.rst1 .. SPDX-License-Identifier: GPL-2.0
12 - Exynos4
13 - Exynos5
14 - STIH4xx HDMI CEC
15 - V4L2 adv7511 (same HW, but a different driver from the drm adv7511)
16 - stm32
17 - Allwinner A10 (sun4i)
18 - Raspberry Pi
19 - dw-hdmi (Synopsis IP)
20 - amlogic (meson ao-cec and ao-cec-g12a)
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/allwinner/
Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
34 #include "sun4i-emac.h"
36 #define DRV_NAME "sun4i-emac"
41 static int debug = -1; /* defaults above */;
52 * The EMAC uses an address register to control where data written
57 * protect the system, but the calls themselves save the address
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
110 if (db->speed == SPEED_100) in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
[all …]

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