| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/starfive/ |
| D | starfive,jh7110-syscon.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
19 - items:
20 - const: starfive,jh7110-sys-syscon
21 - const: syscon
22 - const: simple-mfd
23 - items:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | oxnas,stdclk.txt | 4 Please also refer to clock-bindings.txt in this directory for common clock
8 - compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
9 For OX820, should be "oxsemi,ox820-stdclk"
10 - #clock-cells: 1, see below
13 - compatible: For OX810SE, should be
14 "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
16 "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
20 sys: sys-ctrl@000000 {
21 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
25 compatible = "oxsemi,ox810se-stdclk";
[all …]
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| D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
38 integratorap-cm
41 integratorap-sys
44 integratorap-pci 14 1 14
[all …]
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| D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | oxnas,reset.txt | 8 - compatible: For OX810SE, should be "oxsemi,ox810se-reset"
9 For OX820, should be "oxsemi,ox820-reset"
10 - #reset-cells: 1, see below
13 - compatible: For OX810SE, should be :
14 "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
16 "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"
18 Reset indices are in dt-bindings include files :
19 - For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
20 - For OX820: include/dt-bindings/reset/oxsemi,ox820.h
24 sys: sys-ctrl@000000 {
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | starfive,jh7110-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
38 integratorap-cm
41 integratorap-sys
44 integratorap-pci 14 1 14
[all …]
|
| D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
25 - reg: Must contain the base address and length of the core clock controller.
[all …]
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| D | starfive,jh7110-pll.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 registers in the sys syscon. So the PLLs node should be a child of
13 SYS-SYSCON node.
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
22 const: starfive,jh7110-pll
28 '#clock-cells':
31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
[all …]
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| D | mediatek,mt8365-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markus Schneider-Pargmann <msp@baylibre.com>
20 - enum:
21 - mediatek,mt8365-topckgen
22 - mediatek,mt8365-infracfg
23 - mediatek,mt8365-apmixedsys
24 - mediatek,mt8365-pericfg
[all …]
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| D | mediatek,mt6795-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
20 - enum:
21 - mediatek,mt6795-apmixedsys
22 - mediatek,mt6795-infracfg
23 - mediatek,mt6795-pericfg
[all …]
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| D | mediatek,mt8188-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Garmin Chang <garmin.chang@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
29 - enum:
30 - mediatek,mt8188-apmixedsys
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mt8192-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
19 - enum:
20 - mediatek,mt8192-topckgen
21 - mediatek,mt8192-infracfg
22 - mediatek,mt8192-pericfg
23 - mediatek,mt8192-apmixedsys
[all …]
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| D | mediatek,mt8195-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
27 - enum:
28 - mediatek,mt8195-topckgen
[all …]
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| D | mediatek,mt8186-sys-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
29 - enum:
30 - mediatek,mt8186-mcusys
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
14 a reference to the syscon node (e.g. by phandle, node path, or
20 - Lee Jones <lee@kernel.org>
27 - syscon
30 - compatible
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | oxnas-dwmac.txt | 9 - compatible: For the OX820 SoC, it should be :
10 - "oxsemi,ox820-dwmac" to select glue
11 - "snps,dwmac-3.512" to select IP version.
13 - clocks: Should contain phandles to the following clocks
14 - clock-names: Should contain the following:
15 - "stmmaceth" for the host clock - see stmmac.txt
16 - "gmac" for the peripheral gate clock
18 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
23 compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512";
27 interrupt-names = "macirq", "eth_wake_irq";
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
25 pipe_phy_grf0: syscon@fdc70000 {
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/at91/ |
| D | clk-system.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
10 #include <linux/mfd/syscon.h>
42 struct clk_system *sys = to_clk_system(hw); in clk_system_prepare() local
44 regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); in clk_system_prepare()
46 if (!is_pck(sys->id)) in clk_system_prepare()
49 while (!clk_system_ready(sys->regmap, sys->id)) in clk_system_prepare()
57 struct clk_system *sys = to_clk_system(hw); in clk_system_unprepare() local
59 regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); in clk_system_unprepare()
64 struct clk_system *sys = to_clk_system(hw); in clk_system_is_prepared() local
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/at91/ |
| D | clk-system.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
10 #include <linux/mfd/syscon.h>
43 struct clk_system *sys = to_clk_system(hw); in clk_system_prepare() local
45 regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); in clk_system_prepare()
47 if (!is_pck(sys->id)) in clk_system_prepare()
50 while (!clk_system_ready(sys->regmap, sys->id)) in clk_system_prepare()
58 struct clk_system *sys = to_clk_system(hw); in clk_system_unprepare() local
60 regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); in clk_system_unprepare()
65 struct clk_system *sys = to_clk_system(hw); in clk_system_is_prepared() local
[all …]
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| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| D | imx_rproc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/mfd/syscon.h>
49 * struct imx_rproc_mem - slim internal memory structure
91 /* dev addr , sys addr , size , flags */
92 /* OCRAM_S (M4 Boot code) - alias */
96 /* OCRAM (Code) - alias */
98 /* OCRAM_EPDC (Code) - alias */
100 /* OCRAM_PXP (Code) - alias */
104 /* DDR (Code) - alias, first part of DDR (Data) */
120 /* dev addr , sys addr , size , flags */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | oxnas,pinctrl.txt | 3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
13 - oxsemi,sys-ctrl: a phandle to the system controller syscon node
15 Required properties for pin configuration sub-nodes:
16 - pins: List of pins to which the configuration applies.
18 Optional properties for pin configuration sub-nodes:
19 ----------------------------------------------------
20 - function: Mux function for the specified pins.
21 - bias-pull-up: Enable weak pull-up.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | img,pistachio-gptimer.txt | 1 * Pistachio general-purpose timer based clocksource
4 - compatible: "img,pistachio-gptimer".
5 - reg: Address range of the timer registers.
6 - interrupts: An interrupt for each of the four timers
7 - clocks: Should contain a clock specifier for each entry in clock-names
8 - clock-names: Should contain the following entries:
9 "sys", interface clock
12 - img,cr-periph: Must contain a phandle to the peripheral control
13 syscon node.
17 compatible = "img,pistachio-gptimer";
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | img,pistachio-gptimer.txt | 1 * Pistachio general-purpose timer based clocksource
4 - compatible: "img,pistachio-gptimer".
5 - reg: Address range of the timer registers.
6 - interrupts: An interrupt for each of the four timers
7 - clocks: Should contain a clock specifier for each entry in clock-names
8 - clock-names: Should contain the following entries:
9 "sys", interface clock
12 - img,cr-periph: Must contain a phandle to the peripheral control
13 syscon node.
17 compatible = "img,pistachio-gptimer";
[all …]
|