Searched +full:syscon +full:- +full:uhs +full:- +full:mode (Results 1 – 25 of 27) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/ |
| D | socionext,uniphier-sd.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Masahiro Yamada <yamada.masahiro@socionext.com> 16 - socionext,uniphier-sd-v2.91 17 - socionext,uniphier-sd-v3.1 18 - socionext,uniphier-sd-v3.1.1 32 dma-names: 33 const: rx-tx [all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/socionext/ |
| D | uniphier-sld8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "socionext,uniphier-sld8"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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| D | uniphier-pro4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "socionext,uniphier-pro4"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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| D | uniphier-pxs2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-pxs2"; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; [all …]
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| D | uniphier-pro5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 compatible = "socionext,uniphier-pro5"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 #address-cells = <1>; 17 #size-cells = <0>; 21 compatible = "arm,cortex-a9"; 24 enable-method = "psci"; [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/ |
| D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 20 #address-cells = <2>; [all …]
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| D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 14 compatible = "socionext,uniphier-ld20"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; [all …]
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| D | uniphier-sd.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // Copyright (C) 2017-2018 Socionext Inc. 10 #include <linux/dma-mapping.h> 11 #include <linux/mfd/syscon.h> 59 * IP is extended to support various features: built-in DMA engine, 63 /* RX channel of the built-in DMA controller is broken (Pro5) */ 84 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); in uniphier_sd_priv() 99 dma_async_issue_pending(priv->chan); in uniphier_sd_external_dma_issue() 109 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, in uniphier_sd_external_dma_callback() 110 priv->dma_dir); in uniphier_sd_external_dma_callback() [all …]
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| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 9 * Based on sdhci-of-esdhc.c 18 #include <linux/clk-provider.h> 19 #include <linux/mfd/syscon.h> 26 #include <linux/firmware/xlnx-zynqmp.h> 29 #include "sdhci-cqhci.h" 30 #include "sdhci-pltfm.h" 92 * On some SoCs the syscon area has a feature where the upper 16-bits of 93 * each 32-bit register act as a write mask for the lower 16-bits. This allows [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/ |
| D | hi3660-hikey960.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 12 #include "hikey960-pinctrl.dtsi" 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/interrupt-controller/irq.h> 16 #include <dt-bindings/usb/pd.h> 20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; 35 stdout-path = "serial6:115200n8"; 44 reserved-memory { [all …]
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| D | hi6220-hikey.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 11 #include "hikey-pinctrl.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 16 compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; 26 stdout-path = "serial3:115200n8"; 32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using 33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason 34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data 35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hi3660-hikey960.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 12 #include "hikey960-pinctrl.dtsi" 13 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/interrupt-controller/irq.h> 16 #include <dt-bindings/usb/pd.h> 20 compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; 35 stdout-path = "serial6:115200n8"; 44 reserved-memory { [all …]
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| D | hi6220-hikey.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 11 #include "hikey-pinctrl.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 16 compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; 26 stdout-path = "serial3:115200n8"; 32 * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using 33 * 0x05f0,1000 - 0x05f0,1fff: Reboot reason 34 * 0x06df,f000 - 0x06df,ffff: Mailbox message data 35 * 0x0740,f000 - 0x0740,ffff: MCU firmware section [all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | uniphier-pro4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 11 compatible = "socionext,uniphier-pro4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 #address-cells = <1>; 17 #size-cells = <0>; 21 compatible = "arm,cortex-a9"; 23 enable-method = "psci"; [all …]
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| D | uniphier-pxs2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/thermal/thermal.h> 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/ |
| D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-pxs3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <0>; [all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 9 * Based on sdhci-of-esdhc.c 18 #include <linux/clk-provider.h> 19 #include <linux/mfd/syscon.h> 25 #include <linux/firmware/xlnx-zynqmp.h> 28 #include "sdhci-cqhci.h" 29 #include "sdhci-pltfm.h" 56 * On some SoCs the syscon area has a feature where the upper 16-bits of 57 * each 32-bit register act as a write mask for the lower 16-bits. This allows [all …]
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| /kernel/linux/linux-5.10/arch/mips/boot/dts/brcm/ |
| D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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| D | bcm7435.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <175625000>; 42 cpu_intc: interrupt-controller { 43 #address-cells = <0>; 44 compatible = "mti,cpu-interrupt-controller"; 46 interrupt-controller; [all …]
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| /kernel/linux/linux-6.6/arch/mips/boot/dts/brcm/ |
| D | bcm7435.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <175625000>; 42 cpu_intc: interrupt-controller { 43 #address-cells = <0>; 44 compatible = "mti,cpu-interrupt-controller"; 46 interrupt-controller; [all …]
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| D | bcm7425.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #address-cells = <1>; 4 #size-cells = <1>; 8 #address-cells = <1>; 9 #size-cells = <0>; 11 mips-hpt-frequency = <163125000>; 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 34 interrupt-controller; [all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt8173-elm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/input/linux-event-codes.h> 8 #include <dt-bindings/regulator/dlg,da9211-regulator.h> 9 #include <dt-bindings/gpio/gpio.h> 25 compatible = "pwm-backlight"; 27 power-supply = <&bl_fixed_reg>; 28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&panel_backlight_en_pins>; [all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8173-elm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/input/linux-event-codes.h> 8 #include <dt-bindings/regulator/dlg,da9211-regulator.h> 9 #include <dt-bindings/gpio/gpio.h> 19 compatible = "pwm-backlight"; 21 power-supply = <&bl_fixed_reg>; 22 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&disp_pwm0_pins>; [all …]
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch | 7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470 9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig 11 --- a/drivers/misc/Kconfig 13 @@ -314,6 +314,26 @@ config ISL29020 40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile 42 --- a/drivers/misc/Makefile 44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o 45 obj-$(CONFIG_PHANTOM) += phantom.o 46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o 47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o [all …]
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| /kernel/linux/patches/linux-5.10/yangfan_patch/ |
| D | drivers.patch | 1 diff --git a/drivers/Makefile b/drivers/Makefile 3 --- a/drivers/Makefile 5 @@ -6,6 +6,8 @@ 6 # Rewritten to use lists instead of if-statements. 11 obj-y += irqchip/ 12 obj-y += bus/ 14 diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c 16 --- a/drivers/block/nbd.c 18 @@ -2398,12 +2398,6 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info) 22 - if (!dev_list) { [all …]
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