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Searched +full:tegra194 +full:- +full:ccplex (Results 1 – 13 of 13) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Dnvidia,tegra194-ccplex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 CPU Complex
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
12 - Sumit Gupta <sumitg@nvidia.com>
15 Tegra194 SOC has homogeneous architecture where each cluster has two
25 - nvidia,tegra194-ccplex
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dnvidia,tegra194-ccplex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: NVIDIA Tegra194 CPU Complex device tree bindings
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
12 - Sumit Gupta <sumitg@nvidia.com>
15 Tegra194 SOC has homogeneous architecture where each cluster has two
25 - nvidia,tegra194-ccplex
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 CBB 1.0
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
29 errors due to illegal accesses from CCPLEX are reported by interrupts.
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/kernel/linux/linux-6.6/drivers/cpufreq/
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
9 #include <linux/dma-mapping.h>
20 #include <soc/tegra/bpmp-abi.h>
32 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu))
36 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
83 dev = get_cpu_device(policy->cpu); in tegra_cpufreq_set_bw()
85 return -ENODEV; in tegra_cpufreq_set_bw()
93 data->icc_dram_bw_scaling = false; in tegra_cpufreq_set_bw()
123 mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; in tegra234_get_cpu_ndiv()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/reset/tegra234-reset.h>
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 compatible = "simple-bus";
16 #address-cells = <1>;
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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/kernel/linux/linux-5.10/drivers/mailbox/
Dtegra-hsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
18 #include <dt-bindings/mailbox/tegra186-hsp.h>
111 return readl(hsp->regs + offset); in tegra_hsp_readl()
117 writel(value, hsp->regs + offset); in tegra_hsp_writel()
123 return readl(channel->regs + offset); in tegra_hsp_channel_readl()
129 writel(value, channel->regs + offset); in tegra_hsp_channel_writel()
136 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); in tegra_hsp_doorbell_can_ring()
146 list_for_each_entry(entry, &hsp->doorbells, list) in __tegra_hsp_doorbell_get()
147 if (entry->master == master) in __tegra_hsp_doorbell_get()
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/kernel/linux/linux-5.10/drivers/cpufreq/
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
67 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
110 c = &read_counters_work->c; in tegra_read_counters()
113 c->last_refclk_cnt = lower_32_bits(val); in tegra_read_counters()
114 c->last_coreclk_cnt = upper_32_bits(val); in tegra_read_counters()
115 udelay(c->delay); in tegra_read_counters()
117 c->refclk_cnt = lower_32_bits(val); in tegra_read_counters()
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/kernel/linux/linux-6.6/drivers/mailbox/
Dtegra-hsp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
17 #include <dt-bindings/mailbox/tegra186-hsp.h>
136 return readl(hsp->regs + offset); in tegra_hsp_readl()
142 writel(value, hsp->regs + offset); in tegra_hsp_writel()
148 return readl(channel->regs + offset); in tegra_hsp_channel_readl()
154 writel(value, channel->regs + offset); in tegra_hsp_channel_writel()
161 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE); in tegra_hsp_doorbell_can_ring()
171 list_for_each_entry(entry, &hsp->doorbells, list) in __tegra_hsp_doorbell_get()
172 if (entry->master == master) in __tegra_hsp_doorbell_get()
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/kernel/linux/linux-6.6/drivers/soc/tegra/fuse/
Dfuse-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
52 { .compatible = "nvidia,tegra20-car", },
53 { .compatible = "nvidia,tegra30-car", },
54 { .compatible = "nvidia,tegra114-car", },
55 { .compatible = "nvidia,tegra124-car", },
56 { .compatible = "nvidia,tegra132-car", },
57 { .compatible = "nvidia,tegra210-car", },
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/kernel/linux/linux-6.6/drivers/soc/tegra/cbb/
Dtegra194-cbb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved
25 #include <soc/tegra/tegra-cbb.h>
113 bool format; // [31] = 1 -> FlexNoC versions 2.7 & above
185 "RD - Read, Incrementing",
186 "RDW - Read, Wrap", /* Not Supported */
187 "RDX - Exclusive Read", /* Not Supported */
188 "RDL - Linked Read", /* Not Supported */
189 "WR - Write, Incrementing",
190 "WRW - Write, Wrap", /* Not Supported */
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