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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
8 - reg : Should contain 1 register ranges(address and length). For
9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
13 Example (for a Tegra20 chip):
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-ahb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra AHB
16 - enum:
17 - nvidia,tegra20-ahb
18 - nvidia,tegra30-ahb
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nvidia,tegra20-ehci
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/drivers/amba/
Dtegra-ahb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
81 * whether the passed-in physical address is incorrect, and if so, to
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
[all …]
/kernel/linux/linux-5.10/drivers/amba/
Dtegra-ahb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
81 * whether the passed-in physical address is incorrect, and if so, to
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dci-hdrc-usb2.txt4 - compatible: should be one of:
5 "fsl,imx23-usb"
6 "fsl,imx27-usb"
7 "fsl,imx28-usb"
8 "fsl,imx6q-usb"
9 "fsl,imx6sl-usb"
10 "fsl,imx6sx-usb"
11 "fsl,imx6ul-usb"
12 "fsl,imx7d-usb"
13 "fsl,imx7ulp-usb"
[all …]
/kernel/linux/linux-6.6/drivers/usb/chipidea/
Dci_hdrc_tegra.c1 // SPDX-License-Identifier: GPL-2.0
77 .compatible = "nvidia,tegra20-ehci",
80 .compatible = "nvidia,tegra30-ehci",
83 .compatible = "nvidia,tegra20-udc",
86 .compatible = "nvidia,tegra30-udc",
89 .compatible = "nvidia,tegra114-udc",
92 .compatible = "nvidia,tegra124-udc",
112 phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0); in tegra_usb_reset_controller()
114 return -ENOENT; in tegra_usb_reset_controller()
121 rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads"); in tegra_usb_reset_controller()
[all …]
/kernel/linux/linux-5.10/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
89 tristate "Atmel AHB DMA support"
93 Support the Atmel AHB DMA controller.
103 tristate "Analog Devices AXI-DMAC DMA support"
109 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
129 bool "ST-Ericsson COH901318 DMA support"
133 Enable support for ST-Ericsson COH 901 318 DMA.
152 tristate "SA-11x0 DMA support"
157 Support the DMA engine found on Intel StrongARM SA-1100 and
158 SA-1110 SoCs. This DMA engine can only be used with on-chip
[all …]
Dtegra20-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA driver for Nvidia's Tegra20 APB DMA controller.
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
65 /* AHB memory address */
68 /* AHB sequence register */
104 * on-flight burst and update DMA status register.
145 * sub-transfer as per requester details and hw support.
202 /* Channel-slave specific configuration */
233 writel(val, tdma->base_addr + reg); in tdma_write()
[all …]
/kernel/linux/linux-6.6/drivers/rtc/
Drtc-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
58 * RTC hardware is busy when it is updating its values over AHB once every
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
85 * updated seconds+msec registers to AHB side. in tegra_rtc_wait_while_busy()
88 if (!retries--) in tegra_rtc_wait_while_busy()
99 return -ETIMEDOUT; in tegra_rtc_wait_while_busy()
112 spin_lock_irqsave(&info->lock, flags); in tegra_rtc_read_time()
[all …]
/kernel/linux/linux-5.10/drivers/rtc/
Drtc-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
58 * RTC hardware is busy when it is updating its values over AHB once every
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
85 * updated seconds+msec registers to AHB side. in tegra_rtc_wait_while_busy()
88 if (!retries--) in tegra_rtc_wait_while_busy()
99 return -ETIMEDOUT; in tegra_rtc_wait_while_busy()
112 spin_lock_irqsave(&info->lock, flags); in tegra_rtc_read_time()
[all …]
/kernel/linux/linux-6.6/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
97 tristate "Atmel AHB DMA support"
102 Support the Atmel AHB DMA controller.
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
[all …]
Dtegra20-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA driver for Nvidia's Tegra20 APB DMA controller.
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
64 /* AHB memory address */
67 /* AHB sequence register */
103 * on-flight burst and update DMA status register.
144 * sub-transfer as per requester details and hw support.
201 /* Channel-slave specific configuration */
232 writel(val, tdma->base_addr + reg); in tdma_write()
[all …]
/kernel/linux/linux-6.6/drivers/iommu/
Dtegra-gart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Graphics Address Relocation Table on Tegra20
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
23 #define GART_CONFIG (0x24 - GART_REG_BASE)
24 #define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
25 #define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
54 * Any interaction between any block on PPSB and a block on APB or AHB
55 * must have these read-back to ensure the APB/AHB bus transaction is
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG)
61 for (iova = gart->iovmm_base; \
[all …]
/kernel/linux/linux-5.10/drivers/iommu/
Dtegra-gart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Graphics Address Relocation Table on Tegra20
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
23 #define GART_CONFIG (0x24 - GART_REG_BASE)
24 #define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
25 #define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
54 * Any interaction between any block on PPSB and a block on APB or AHB
55 * must have these read-back to ensure the APB/AHB bus transaction is
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG)
61 for (iova = gart->iovmm_base; \
[all …]
/kernel/linux/linux-5.10/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
111 supports spi-mem interface.
181 this code to manage the per-word or per-transfer accesses to the
211 Flash over 1/2/4-bit wide bus. Enable this option if you have a
219 This enables dedicated general purpose SPI/Microwire1-compatible
220 master mode interface (SSI1) for CLPS711X-based CPUs.
[all …]
/kernel/linux/linux-6.6/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
145 supports spi-mem interface.
224 this code to manage the per-word or per-transfer accesses to the
254 Flash over 1/2/4-bit wide bus. Enable this option if you have a
266 Flash over up to 8-bit wide bus. Enable this option if you have a
274 This enables dedicated general purpose SPI/Microwire1-compatible
[all …]
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch1 diff --git a/drivers/Makefile b/drivers/Makefile
3 --- a/drivers/Makefile
5 @@ -6,6 +6,8 @@
6 # Rewritten to use lists instead of if-statements.
11 obj-y += irqchip/
12 obj-y += bus/
14 diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
16 --- a/drivers/block/nbd.c
18 @@ -2398,12 +2398,6 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info)
22 - if (!dev_list) {
[all …]