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Searched +full:tegra20 +full:- +full:epp (Results 1 – 11 of 11) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-epp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Encoder Pre-Processor
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^epp@[0-9a-f]+$"
19 - nvidia,tegra20-epp
20 - nvidia,tegra30-epp
[all …]
Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/memory/tegra20-mc.h>
184 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
204 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
206 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
207 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
209 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
220 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
222 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
223 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
[all …]
/kernel/linux/linux-6.6/drivers/clk/tegra/
Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/tegra20-car.h>
18 #include "clk-id.h"
444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
450 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
451 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
[all …]
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/tegra20-car.h>
16 #include "clk-id.h"
442 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
443 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
444 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
446 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
448 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
449 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <dt-bindings/memory/tegra20-mc.h>
265 TEGRA20_MC_RESET(EPP, 0x100, 0x14c, 0x104, 3),
285 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
287 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
288 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
290 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
301 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_deassert()
303 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_deassert()
304 mc_writel(mc, value | BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_deassert()
[all …]