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Searched +full:tegra20 +full:- +full:mc +full:- +full:gart (Results 1 – 11 of 11) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-mc.txt1 NVIDIA Tegra20 MC(Memory Controller)
4 - compatible : "nvidia,tegra20-mc-gart"
5 - reg : Should contain 2 register ranges: physical base address and length of
6 the controller's registers and the GART aperture respectively.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clocks/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - mc: the module's clock input
11 - interrupts : Should contain MC General interrupt.
12 - #reset-cells : Should be 1. This cell represents memory client module ID.
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
18 has a configurable arbitration algorithm to allow the user to fine-tune
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/kernel/linux/linux-5.10/drivers/devfreq/
Dtegra20-devfreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * NVIDIA Tegra20 devfreq driver
5 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <soc/tegra/mc.h>
41 struct devfreq *devfreq = tegra->devfreq; in tegra_devfreq_target()
53 err = clk_set_min_rate(tegra->emc_clock, rate); in tegra_devfreq_target()
57 err = clk_set_rate(tegra->emc_clock, 0); in tegra_devfreq_target()
64 clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); in tegra_devfreq_target()
84 stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); in tegra_devfreq_get_dev_status()
85 stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; in tegra_devfreq_get_dev_status()
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/kernel/linux/linux-5.10/drivers/iommu/
Dtegra-gart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Graphics Address Relocation Table on Tegra20
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
10 #define dev_fmt(fmt) "gart: " fmt
20 #include <soc/tegra/mc.h>
23 #define GART_CONFIG (0x24 - GART_REG_BASE)
24 #define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
25 #define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
55 * must have these read-back to ensure the APB/AHB bus transaction is
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG) argument
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/kernel/linux/linux-6.6/drivers/iommu/
Dtegra-gart.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Graphics Address Relocation Table on Tegra20
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
10 #define dev_fmt(fmt) "gart: " fmt
20 #include <soc/tegra/mc.h>
23 #define GART_CONFIG (0x24 - GART_REG_BASE)
24 #define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
25 #define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
55 * must have these read-back to ensure the APB/AHB bus transaction is
58 #define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG) argument
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/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
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/kernel/linux/linux-5.10/drivers/memory/tegra/
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
20 #include "mc.h"
24 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
27 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
30 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
33 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
36 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
39 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
45 static int tegra_mc_block_dma_common(struct tegra_mc *mc, in tegra_mc_block_dma_common() argument
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/kernel/linux/linux-6.6/drivers/memory/tegra/
Dmc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
18 #include <linux/tegra-icc.h>
22 #include "mc.h"
26 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
29 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
32 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
35 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
38 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
41 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
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Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <dt-bindings/memory/tegra20-mc.h>
16 #include "mc.h"
75 const struct tegra_mc *mc; member
279 static int tegra20_mc_hotreset_assert(struct tegra_mc *mc, in tegra20_mc_hotreset_assert() argument
285 spin_lock_irqsave(&mc->lock, flags); in tegra20_mc_hotreset_assert()
287 value = mc_readl(mc, rst->reset); in tegra20_mc_hotreset_assert()
288 mc_writel(mc, value & ~BIT(rst->bit), rst->reset); in tegra20_mc_hotreset_assert()
290 spin_unlock_irqrestore(&mc->lock, flags); in tegra20_mc_hotreset_assert()
295 static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc, in tegra20_mc_hotreset_deassert() argument
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/kernel/linux/linux-6.6/drivers/gpu/host1x/
Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
10 #include <linux/dma-mapping.h>
27 #include <asm/dma-iommu.h>
47 writel(v, host1x->common_regs + r); in host1x_common_writel()
52 writel(v, host1x->hv_regs + r); in host1x_hypervisor_writel()
57 return readl(host1x->hv_regs + r); in host1x_hypervisor_readl()
62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_writel()
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; in host1x_sync_readl()
76 writel(v, ch->regs + r); in host1x_ch_writel()
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