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/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
14 * with a timer counter that goes up. When it overflows it gets
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
26 * can get updated as below based on the current timer counter:
[all …]
Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
24 #define TPU_TSTR 0x00 /* Timer start register (shared) */
26 #define TPU_TCRn 0x00 /* Timer control register */
35 #define TPU_TMDRn 0x04 /* Timer mode register */
41 #define TPU_TIORn 0x08 /* Timer I/O control register */
50 #define TPU_TIERn 0x0c /* Timer interrupt enable register */
51 #define TPU_TSRn 0x10 /* Timer status register */
52 #define TPU_TCNTn 0x14 /* Timer counter */
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
14 * with a timer counter that goes up. When it overflows it gets
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
26 * can get updated as below based on the current timer counter:
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
[all …]
Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
18 #include <linux/pwm.h>
24 #define TPU_TSTR 0x00 /* Timer start register (shared) */
26 #define TPU_TCRn 0x00 /* Timer control register */
35 #define TPU_TMDRn 0x04 /* Timer mode register */
41 #define TPU_TIORn 0x08 /* Timer I/O control register */
50 #define TPU_TIERn 0x0c /* Timer interrupt enable register */
51 #define TPU_TSRn 0x10 /* Timer status register */
52 #define TPU_TCNTn 0x14 /* Timer counter */
[all …]
/kernel/linux/linux-5.10/arch/mips/loongson32/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
39 bool "Use PWM Timer for clockevent/clocksource"
43 This option changes the default clockevent/clocksource to PWM Timer,
54 bool "Use PWM Timer 0"
56 Use PWM Timer 0 as the default clockevent/clocksourcer.
59 bool "Use PWM Timer 1"
61 Use PWM Timer 1 as the default clockevent/clocksourcer.
64 bool "Use PWM Timer 2"
66 Use PWM Timer 2 as the default clockevent/clocksourcer.
69 bool "Use PWM Timer 3"
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
[all …]
Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/microchip/
Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
[all …]
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/
Dir-rx51.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/pwm.h>
15 #include <media/rc-core.h>
21 struct pwm_device *pwm; member
22 struct hrtimer timer; member
35 pwm_enable(ir_rx51->pwm); in ir_rx51_on()
40 pwm_disable(ir_rx51->pwm); in ir_rx51_off()
45 struct pwm_device *pwm = ir_rx51->pwm; in init_timing_params() local
46 int duty, period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, ir_rx51->freq); in init_timing_params()
48 duty = DIV_ROUND_CLOSEST(ir_rx51->duty_cycle * period, 100); in init_timing_params()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This hardware block provides 3 types of timer along with PWM functionality:
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
12 by a programmable prescaler, break input feature, PWM outputs and
13 complementary PWM outputs channels.
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
15 driven by a programmable prescaler and PWM outputs.
[all …]
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers bindings
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC PWM timers
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
[all …]
Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
[all …]
Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/drivers/media/rc/
Dir-rx51.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/pwm.h>
15 #include <media/rc-core.h>
21 struct pwm_device *pwm; member
23 struct hrtimer timer; member
36 ir_rx51->state.enabled = true; in ir_rx51_on()
37 pwm_apply_might_sleep(ir_rx51->pwm, &ir_rx51->state); in ir_rx51_on()
42 ir_rx51->state.enabled = false; in ir_rx51_off()
43 pwm_apply_might_sleep(ir_rx51->pwm, &ir_rx51->state); in ir_rx51_off()
48 ir_rx51->state.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, ir_rx51->freq); in init_timing_params()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Timer/Counter Unit (TCU)
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
[all …]
Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32- bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max.
16 - Pulse input 3 lines
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Timer/Counter Unit (TCU) devicetree bindings
11 Documentation/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4770-tcu
[all …]

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