| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | ti,timer.txt | 1 OMAP Timer bindings
4 - compatible: Should be set to one of the below. Please note that
5 OMAP44xx devices have timer instances that are 100%
8 So for OMAP44xx devices timer instances may use
11 ti,omap2420-timer (applicable to OMAP24xx devices)
12 ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
13 ti,omap4430-timer (applicable to OMAP44xx devices)
14 ti,omap5430-timer (applicable to OMAP543x devices)
15 ti,am335x-timer (applicable to AM335x devices)
16 ti,am335x-timer-1ms (applicable to AM335x devices)
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| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/ |
| D | corstone1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
26 #size-cells = <0>;
30 compatible = "arm,cortex-a35";
32 next-level-cache = <&L2_0>;
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/ |
| D | ti,timer-dm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
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| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
7 PIT Timer required properties:
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
13 PIT64B Timer required properties:
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
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| /kernel/linux/linux-6.6/arch/arm/mach-at91/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
147 bool "Periodic Interval Timer (PIT) support"
153 Timer. It has a relatively low resolution and the TC Block clocksource
157 bool "Timer Counter Blocks (TCB) support"
163 On platforms with 16-bit counters, two timer channels are combined
164 to make a single 32-bit timer.
168 bool "64-bit Periodic Interval Timer (PIT64B) support"
173 clocksource and clockevent (SAMA7G5) based on Microchip 64-bit
174 Periodic Interval Timer.
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-shmobile/ |
| D | setup-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
24 #include "rcar-gen2.h"
27 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
32 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-shmobile/ |
| D | setup-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
23 #include "rcar-gen2.h"
26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid"
5 - reg : Should contain registers location and length
7 PIT Timer required properties:
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
13 PIT64B Timer required properties:
14 - compatible: Should be "microchip,sam9x60-pit64b"
15 - reg: Should contain registers location and length
16 - interrupts: Should contain interrupt for PIT64B timer
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | keembay-soc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/intel/ |
| D | keembay-soc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/rtc/ |
| D | rtc-meson-vrtc.txt | 8 - compatible: should be "amlogic,meson-vrtc"
9 - reg: physical address for the alarm register
12 application processors (AP) and the secure co-processor (SCP.) When
14 program an always-on timer before going sleep. When the timer expires,
20 compatible = "amlogic,meson-vrtc";
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/tesla/ |
| D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/rtc/ |
| D | amlogic,meson-vrtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/amlogic,meson-vrtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
17 application processors (AP) and the secure co-processor (SCP.) When
19 program an always-on timer before going sleep. When the timer expires,
23 - $ref: rtc.yaml#
28 - amlogic,meson-vrtc
34 - compatible
[all …]
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| /kernel/linux/linux-6.6/drivers/acpi/arm64/ |
| D | gtdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
26 * @platform_timer: The pointer to the start of Platform Timer Structure
43 platform_timer += gh->length; in next_platform_timer()
58 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
66 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
69 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
89 * Note: Secure state is not managed by the kernel on ARM64 systems.
90 * So we only handle the non-secure timer PPIs,
[all …]
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| /kernel/linux/linux-5.10/drivers/acpi/arm64/ |
| D | gtdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
26 * @platform_timer: The pointer to the start of Platform Timer Structure
43 platform_timer += gh->length; in next_platform_timer()
58 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
66 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
69 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
89 * Note: Secure state is not managed by the kernel on ARM64 systems.
90 * So we only handle the non-secure timer PPIs,
[all …]
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| /kernel/linux/linux-6.6/drivers/clocksource/ |
| D | timer-ti-dm-systimer.c | 1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/clk/clk-conf.h>
17 #include <clocksource/timer-ti-dm.h>
18 #include <dt-bindings/bus/ti-sysc.h>
34 * Subset of the timer registers we use. Note that the register offsets
35 * depend on the timer revision detected.
68 u32 tidr = readl_relaxed(t->base); in dmtimer_systimer_revision1()
82 writel_relaxed(val, t->base + t->sysc); in dmtimer_systimer_enable()
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); in dmtimer_systimer_disable()
95 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET; in dmtimer_systimer_type1_reset()
[all …]
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-ti-dm-systimer.c | 1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/clk/clk-conf.h>
17 #include <clocksource/timer-ti-dm.h>
18 #include <dt-bindings/bus/ti-sysc.h>
34 * Subset of the timer registers we use. Note that the register offsets
35 * depend on the timer revision detected.
68 u32 tidr = readl_relaxed(t->base); in dmtimer_systimer_revision1()
82 writel_relaxed(val, t->base + t->sysc); in dmtimer_systimer_enable()
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc); in dmtimer_systimer_disable()
95 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET; in dmtimer_systimer_type1_reset()
[all …]
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| /kernel/linux/linux-6.6/include/dt-bindings/gce/ |
| D | mt8186-gce.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
79 /* VCU: poll with timeout for GPR timer */
351 * Note that token 512 to 639 may set secure
367 /* Notify normal CMDQ there are some secure task done
368 * MUST NOT CHANGE, this token sync with secure world
386 * There are 15 32-bit GPR, 3 GPR form a set
387 * (64-bit for address, 32-bit for value)
400 /* event for gpr timer, used in sleep and poll with timeout */
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | timer.c | 2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
16 * OMAP Dual-mode timer framework support by Timo Teras
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
35 #include "omap-secure.h"
50 * The realtime counter also called master counter, is a free-running
52 * by the CPU local timer peripherals in the MPU cluster. The timer counts
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-y := -I$(srctree)/$(src)/include \
7 -I$(srctree)/arch/arm/plat-omap/include
10 obj-y := id.o io.o control.o devices.o fb.o pm.o \
12 omap_device.o omap-headsmp.o sram.o
14 hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
16 clock-common = clock.o
17 secure-common = omap-smc.o omap-secure.o
19 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
20 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| D | timer.c | 2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
16 * OMAP Dual-mode timer framework support by Timo Teras
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
35 #include "omap-secure.h"
50 * The realtime counter also called master counter, is a free-running
52 * by the CPU local timer peripherals in the MPU cluster. The timer counts
|
| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | keembay_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
61 return readl(wdt->base + offset); in keembay_wdt_readl()
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
67 writel(val, wdt->base + offset); in keembay_wdt_writel()
74 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate); in keembay_wdt_set_timeout_reg()
82 if (wdog->pretimeout) in keembay_wdt_set_pretimeout_reg()
83 th_val = wdog->timeout - wdog->pretimeout; in keembay_wdt_set_pretimeout_reg()
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
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