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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
101 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
105 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
118 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
127 hw->init = &init; in meson8b_dwmac_register_clk()
129 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
135 struct device *dev = dwmac->dev; in meson8b_init_rgmii_tx_clk()
[all …]
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
91 * configured, equals to (plat->variant->num_clks - 1) in default for all the case, in mt2712_set_interface()
94 plat->num_clks_to_config = plat->variant->num_clks - 1; in mt2712_set_interface()
97 switch (plat->phy_mode) { in mt2712_set_interface()
102 if (plat->rmii_clk_from_mac) in mt2712_set_interface()
103 plat->num_clks_to_config++; in mt2712_set_interface()
113 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
114 return -EINVAL; in mt2712_set_interface()
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52 * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
129 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev), in meson8b_dwmac_register_clk()
138 hw->init = &init; in meson8b_dwmac_register_clk()
140 return devm_clk_register(dwmac->dev, hw); in meson8b_dwmac_register_clk()
[all …]
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
150 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/sti/
Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/sti/
Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
58 arg_tmp--; in awg_generate_instr()
105 return -EINVAL; in awg_generate_instr()
108 arg_tmp = arg_tmp - arg; in awg_generate_instr()
113 fwparams->ram_code[fwparams->instruction_offset] = in awg_generate_instr()
115 fwparams->instruction_offset++; in awg_generate_instr()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dst,sta350.txt7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
[all …]
/kernel/linux/linux-6.6/drivers/video/backlight/
Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
45 #define CMD_NULL (-1)
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
105 CMD1(0xd8, 0x01), /* CKV timing control on/off */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
[all …]
/kernel/linux/linux-5.10/drivers/video/backlight/
Dtdo24m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
45 #define CMD_NULL (-1)
92 CMD1(0xd1, 0x01), /* CKV timing control on/off */
93 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
94 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
95 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
96 CMD1(0xd5, 0x14), /* ASW timing control (2) */
105 CMD1(0xd8, 0x01), /* CKV timing control on/off */
106 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
29 …* | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_…
[all …]
/kernel/linux/linux-5.10/net/mac80211/
Dmesh_sync.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012, Pavel Zubarev <pavel.zubarev@gmail.com>
4 * Copyright 2011-2012, Marco Porsch <marco.porsch@s2005.tu-chemnitz.de>
5 * Copyright 2011-2012, cozybit Inc.
10 #include "driver-ops.h"
13 * which we do no TSF adjustment.
19 * introduced by TSF adjustment latency.
36 * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT
42 return (ie->mesh_config->meshconf_cap & in mesh_peer_tbtt_adjusting()
48 struct ieee80211_local *local = sdata->local; in mesh_sync_adjust_tsf()
[all …]
/kernel/linux/linux-6.6/net/mac80211/
Dmesh_sync.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012, Pavel Zubarev <pavel.zubarev@gmail.com>
4 * Copyright 2011-2012, Marco Porsch <marco.porsch@s2005.tu-chemnitz.de>
5 * Copyright 2011-2012, cozybit Inc.
11 #include "driver-ops.h"
14 * which we do no TSF adjustment.
20 * introduced by TSF adjustment latency.
37 * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT
44 (cfg->meshconf_cap & IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING); in mesh_peer_tbtt_adjusting()
49 struct ieee80211_local *local = sdata->local; in mesh_sync_adjust_tsf()
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
86 * according to board actual timing.
117 /* Offset of Timing Adjust register */
127 /* Offset of Logic Timing Adjust register */
131 /* value in Logic Timing Adjustment register */
206 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
208 return -ENOMEM; in xenon_alloc_emmc_phy()
[all …]
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
21 #include "sdhci-pltfm.h"
22 #include "sdhci-xenon.h"
41 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
42 return -ETIMEDOUT; in xenon_enable_internal_clk()
50 /* Set SDCLK-off-while-idle */
91 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
96 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
137 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
87 * according to board actual timing.
120 /* Offset of Timing Adjust register */
130 /* Offset of Logic Timing Adjust register */
134 /* value in Logic Timing Adjustment register */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
[all …]
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include "sdhci-pltfm.h"
23 #include "sdhci-xenon.h"
42 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
43 return -ETIMEDOUT; in xenon_enable_internal_clk()
51 /* Set SDCLK-off-while-idle */
92 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
97 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
138 /* Disable the Re-Tuning Request functionality */ in xenon_retune_setup()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/amlogic/
Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmeson8m2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
19 /delete-node/ video-lut@20;
21 canvas: video-lut@48 {
22 compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
28 compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
35 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
37 reset-names = "stmmaceth";
41 compatible = "amlogic,meson8m2-aobus-pinctrl",
42 "amlogic,meson8-aobus-pinctrl";
[all …]
/kernel/linux/linux-5.10/drivers/iio/proximity/
Dvcnl3020.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define VCNL_PS_MOD_ADJ 0x8f /* Proximity Modulator Timing Adjustment */
36 #define VCNL_PS_OD BIT(3) /* start on-demand proximity
44 * struct vcnl3020_data - vcnl3020 specific data.
58 * struct vcnl3020_property - vcnl3020 property.
79 .name = "vishay,led-current-microamp",
90 rc = device_property_read_u32(data->dev, prop.name, &val); in vcnl3020_get_and_apply_property()
97 rc = regmap_write(data->regmap, prop.reg, val); in vcnl3020_get_and_apply_property()
99 dev_err(data->dev, "Error (%d) setting property (%s)\n", in vcnl3020_get_and_apply_property()
111 rc = regmap_read(data->regmap, VCNL_PROD_REV, &reg); in vcnl3020_init()
[all …]
/kernel/linux/linux-6.6/include/linux/
Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
74 * timing source or cycle counter. Since it will be occurred on every
[all …]
/kernel/linux/linux-5.10/include/linux/
Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */
60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */
73 * when an interrupt takes places versus a high speed, fine-grained
74 * timing source or cycle counter. Since it will be occurred on every
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlegacy/
D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
[all …]

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