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/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/kernel/linux/linux-6.6/mm/
Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/backing-dev.h>
39 #include <linux/memory-tiers.h>
42 #include <asm/tlb.h>
78 if (!vma->vm_mm) /* vdso */ in hugepage_vma_check()
103 !transhuge_vma_suitable(vma, (vma->vm_end - HPAGE_PMD_SIZE))) in hugepage_vma_check()
111 if (!in_pf && shmem_file(vma->vm_file)) in hugepage_vma_check()
112 return shmem_is_huge(file_inode(vma->vm_file), vma->vm_pgoff, in hugepage_vma_check()
113 !enforce_sysfs, vma->vm_mm, vm_flags); in hugepage_vma_check()
138 if (!vma->anon_vma) in hugepage_vma_check()
[all …]
Dmapping_dirty_helpers.c1 // SPDX-License-Identifier: GPL-2.0
11 * struct wp_walk - Private struct for pagetable walk callbacks
25 * wp_pte - Write-protect a pte
31 * The function write-protects a pte and records the range in
32 * virtual address space of touched ptes for efficient range TLB flushes.
37 struct wp_walk *wpwalk = walk->private; in wp_pte()
41 pte_t old_pte = ptep_modify_prot_start(walk->vma, addr, pte); in wp_pte()
44 ptep_modify_prot_commit(walk->vma, addr, pte, old_pte, ptent); in wp_pte()
45 wpwalk->total++; in wp_pte()
46 wpwalk->tlbflush_start = min(wpwalk->tlbflush_start, addr); in wp_pte()
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/mm/
Dtranshuge.rst28 requiring larger clear-page copy-page in page faults which is a
38 1) the TLB miss will run faster (especially with virtualization using
42 2) a single TLB entry will be mapping a much larger amount of virtual
43 memory in turn reducing the number of TLB misses. With
44 virtualization and nested pagetables the TLB can be mapped of
47 the two is using hugepages just because of the fact the TLB miss is
78 possible to disable hugepages system-wide and to only have them inside
95 -------------------
149 should be self-explanatory.
168 -------------------
[all …]
/kernel/linux/linux-5.10/mm/
Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
37 #include <asm/tlb.h>
68 return transhuge_vma_enabled(vma, vma->vm_flags) && vma->vm_file && in file_thp_enabled()
69 !inode_is_open_for_write(vma->vm_file->f_inode) && in file_thp_enabled()
70 (vma->vm_flags & VM_EXEC); in file_thp_enabled()
76 unsigned long addr = (vma->vm_end & HPAGE_PMD_MASK) - HPAGE_PMD_SIZE; in transparent_hugepage_active()
129 if (test_bit(MMF_HUGE_ZERO_PAGE, &mm->flags)) in mm_get_huge_zero_page()
135 if (test_and_set_bit(MMF_HUGE_ZERO_PAGE, &mm->flags)) in mm_get_huge_zero_page()
143 if (test_bit(MMF_HUGE_ZERO_PAGE, &mm->flags)) in mm_put_huge_zero_page()
202 ret = -EINVAL; in enabled_store()
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
Dtlb-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
[all …]
Dtlb-v4wbi.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 and version 5 TLB handling functions.
8 * These assume a split I/D TLBs, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
22 * Invalidate a range of TLB entries in the specified address space.
24 * - start - range start address
25 * - end - range end address
26 * - mm - mm_struct describing address space
[all …]
Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
14 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
19 .arch armv7-a
24 * Invalidate a range of TLB entries in the specified address space.
26 * - start - start address (may not be aligned)
[all …]
Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
12 #include <asm/asm-offsets.h>
16 #include "proc-macros.S"
25 * Invalidate a range of TLB entries in the specified address space.
27 * - start - start address (may not be aligned)
28 * - end - end address (exclusive, may not be aligned)
[all …]
Dtlb-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs, and no write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified user address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
[all …]
/kernel/linux/linux-5.10/arch/arm/mm/
Dtlb-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
[all …]
Dtlb-v4wbi.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 and version 5 TLB handling functions.
8 * These assume a split I/D TLBs, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
22 * Invalidate a range of TLB entries in the specified address space.
24 * - start - range start address
25 * - end - range end address
26 * - mm - mm_struct describing address space
[all …]
Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
14 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
22 * Invalidate a range of TLB entries in the specified address space.
24 * - start - start address (may not be aligned)
25 * - end - end address (exclusive, may not be aligned)
[all …]
Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
12 #include <asm/asm-offsets.h>
16 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - start address (may not be aligned)
26 * - end - end address (exclusive, may not be aligned)
[all …]
Dtlb-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs, and no write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified user address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
[all …]
/kernel/linux/linux-6.6/Documentation/admin-guide/mm/
Dtranshuge.rst26 requiring larger clear-page copy-page in page faults which is a
36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
76 possible to disable hugepages system-wide and to only have them inside
93 -------------------
147 should be self-explanatory.
166 -------------------
[all …]
/kernel/linux/linux-5.10/arch/arc/include/asm/
Dpgalloc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -"/proc/meminfo | grep PageTables" kept on increasing
10 * -Variable pg-sz means that Page Tables could be variable sized themselves
11 * So calculate it based on addr traversal split [pgd-bits:pte-bits:xxx]
12 * -Page Table size capped to max 1 to save memory - hence verified.
13 * -Since these deal with constants, gcc compile-time optimizes them.
16 * -Added pgtable ctor/dtor used for pgtable mem accounting
19 * -Switched pgtable_t from being struct page * to unsigned long
24 * pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate)
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
[all …]
/kernel/linux/linux-5.10/arch/mips/mm/
Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
53 * TLB load/store/modify handlers.
132 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
136 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
231 * TLB exception handlers.
263 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
280 /* The only general purpose registers allowed in TLB handlers. */
308 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
[all …]
/kernel/linux/linux-6.6/arch/mips/mm/
Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
52 * TLB load/store/modify handlers.
131 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
135 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
230 * TLB exception handlers.
262 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
279 /* The only general purpose registers allowed in TLB handlers. */
307 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
[all …]
/kernel/linux/linux-6.6/arch/sh/mm/
Dtlb-pteaex.c2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
42 * For the extended mode TLB this is trivial, only the ESZ and in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
58 /* Load the TLB */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
86 * Flush all the TLB. in local_flush_tlb_all()
/kernel/linux/linux-5.10/arch/sh/mm/
Dtlb-pteaex.c2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
42 * For the extended mode TLB this is trivial, only the ESZ and in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
58 /* Load the TLB */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
86 * Flush all the TLB. in local_flush_tlb_all()

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