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Searched full:tmclk (Results 1 – 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-tegra.c154 struct clk *tmclk; member
1668 * timeout clock and SW can choose TMCLK or SDCLK for hardware in sdhci_tegra_probe()
1673 * 12Mhz TMCLK which is advertised in host capability register. in sdhci_tegra_probe()
1674 * With TMCLK of 12Mhz provides maximum data timeout period that can in sdhci_tegra_probe()
1677 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's in sdhci_tegra_probe()
1678 * supporting separate TMCLK. in sdhci_tegra_probe()
1682 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1688 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1696 "failed to enable tmclk: %d\n", rc); in sdhci_tegra_probe()
1700 tegra_host->tmclk = clk; in sdhci_tegra_probe()
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Dsdhci.h417 /* Controller uses SDCLK instead of TMCLK for data timeouts */
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-tegra.c164 struct clk *tmclk; member
1724 * timeout clock and SW can choose TMCLK or SDCLK for hardware in sdhci_tegra_probe()
1729 * 12Mhz TMCLK which is advertised in host capability register. in sdhci_tegra_probe()
1730 * With TMCLK of 12Mhz provides maximum data timeout period that can in sdhci_tegra_probe()
1733 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's in sdhci_tegra_probe()
1734 * supporting separate TMCLK. in sdhci_tegra_probe()
1738 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1744 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1752 "failed to enable tmclk: %d\n", rc); in sdhci_tegra_probe()
1756 tegra_host->tmclk = clk; in sdhci_tegra_probe()
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Dsdhci.h428 /* Controller uses SDCLK instead of TMCLK for data timeouts */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt23 strings 'sdhci' and 'tmclk' to represent the module and
132 clock-names = "sdhci", "tmclk";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.yaml214 - const: tmclk
293 clock-names = "sdhci", "tmclk";
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml188 clock-names = "sdhci", "tmclk";
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi557 clock-names = "sdhci", "tmclk";
587 clock-names = "sdhci", "tmclk";
612 clock-names = "sdhci", "tmclk";
639 clock-names = "sdhci", "tmclk";
Dtegra210.dtsi1202 clock-names = "sdhci", "tmclk";
1231 clock-names = "sdhci", "tmclk";
1249 clock-names = "sdhci", "tmclk";
1273 clock-names = "sdhci", "tmclk";
Dtegra194.dtsi702 clock-names = "sdhci", "tmclk";
728 clock-names = "sdhci", "tmclk";
755 clock-names = "sdhci", "tmclk";
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1208 clock-names = "sdhci", "tmclk";
1237 clock-names = "sdhci", "tmclk";
1255 clock-names = "sdhci", "tmclk";
1279 clock-names = "sdhci", "tmclk";
Dtegra186.dtsi846 clock-names = "sdhci", "tmclk";
876 clock-names = "sdhci", "tmclk";
901 clock-names = "sdhci", "tmclk";
928 clock-names = "sdhci", "tmclk";
Dtegra194.dtsi1018 clock-names = "sdhci", "tmclk";
1057 clock-names = "sdhci", "tmclk";
1097 clock-names = "sdhci", "tmclk";
Dtegra234.dtsi961 clock-names = "sdhci", "tmclk";
996 clock-names = "sdhci", "tmclk";
/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch13367 - struct clk *tmclk;
13618 - * timeout clock and SW can choose TMCLK or SDCLK for hardware
13623 - * 12Mhz TMCLK which is advertised in host capability register.
13624 - * With TMCLK of 12Mhz provides maximum data timeout period that can
13627 - * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
13628 - * supporting separate TMCLK.
13632 - clk = devm_clk_get(&pdev->dev, "tmclk");
13638 - dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
13646 - "failed to enable tmclk: %d\n", rc);
13650 - tegra_host->tmclk = clk;
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